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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 09:56:52 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | a85c55113fbaf62ade66e583942782820fd0e9ff (patch) | |
| tree | ce17ee222a79c358b9eac894ddc8f6deab0ac5f4 | |
| parent | 8408c13405bfe561e6a6022e2730ecca18a1464a (diff) | |
| download | yosys-a85c55113fbaf62ade66e583942782820fd0e9ff.tar.gz yosys-a85c55113fbaf62ade66e583942782820fd0e9ff.tar.bz2 yosys-a85c55113fbaf62ade66e583942782820fd0e9ff.zip | |
synth_ecp5: use +/abc9_model.v
| -rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 463ddb5ca..9916fdafb 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -322,7 +322,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap " + techmap_args); if (abc9) { - run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v"); + run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v"); if (nowidelut) run("abc9 -maxlut 4 -W 200"); else |