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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-18 14:31:24 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 88d5997c80e5c2bebb479f76b123899c6de48c57 (patch) | |
| tree | 0143966903cf2127e63976f0b1264c625978c904 | |
| parent | 376319dc8d96b7592cda5c0249228dd6a26ea5a7 (diff) | |
| download | yosys-88d5997c80e5c2bebb479f76b123899c6de48c57.tar.gz yosys-88d5997c80e5c2bebb479f76b123899c6de48c57.tar.bz2 yosys-88d5997c80e5c2bebb479f76b123899c6de48c57.zip | |
abc9_ops: suppress -prep_box warning for abc9_flop
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index e46ad0a02..cffcc189e 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -670,7 +670,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode) ss << std::endl; auto &t = timing.setup_module(module).comb; - if (t.empty()) + if (!abc9_flop && t.empty()) log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module)); for (const auto &o : outputs) { |