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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-11 09:18:08 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 3d6603792dbd36ccb572403815b78121a7ad80e8 (patch) | |
| tree | 7795e5b93c302d6881e3320b3b3059939899f268 | |
| parent | 74f49b1f55e08c9939c9e0c8a1a5c0405f0d28c5 (diff) | |
| download | yosys-3d6603792dbd36ccb572403815b78121a7ad80e8.tar.gz yosys-3d6603792dbd36ccb572403815b78121a7ad80e8.tar.bz2 yosys-3d6603792dbd36ccb572403815b78121a7ad80e8.zip | |
abc9_ops: assert on $specify2 properties
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index d08c42e3b..52beae421 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -572,7 +572,10 @@ void prep_lut(RTLIL::Design *design, int maxlut) continue; log_assert(cell->getParam(ID(SRC_WIDTH)) == 1); log_assert(cell->getParam(ID(DST_WIDTH)) == 1); + SigBit s = cell->getPort(ID(SRC)); SigBit d = cell->getPort(ID(DST)); + log_assert(s.wire->port_input); + log_assert(d.wire->port_output); if (o == SigBit()) o = d; else |