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* New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-213-0/+149
* Merge pull request #1621 from YosysHQ/clifford/fminitClaire Wolf2020-01-202-0/+198
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| * Add fminit passClifford Wolf2020-01-092-0/+198
* | Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_mapEddie Hung2020-01-182-125/+88
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| * | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623Eddie Hung2020-01-172-119/+82
| * | +/xilinx/arith_map.v fix $lcu ruleEddie Hung2020-01-171-6/+6
* | | Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warningDavid Shah2020-01-181-2/+8
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| * | | ice40: Demote conflicting FF init values to a warningNiklas Nisbeth2019-12-311-2/+8
* | | | Merge pull request #1645 from YosysHQ/eddie/fix1644Eddie Hung2020-01-179-20/+52
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| * | | xilinx_dsp: another typo; move xilinx specific testEddie Hung2020-01-172-1/+1
| * | | ice40_dsp: fix typoEddie Hung2020-01-172-2/+13
| * | | ConsistencyEddie Hung2020-01-172-4/+6
| * | | xilinx_dsp: add parameter defaultsEddie Hung2020-01-171-7/+7
| * | | Add #1644 testcaseEddie Hung2020-01-172-0/+2
| * | | synth_ice40: call wreduce before mul2dspEddie Hung2020-01-171-1/+2
| * | | ice40_dsp: add testEddie Hung2020-01-171-0/+11
| * | | ice40_dsp: add default values for parametersEddie Hung2020-01-172-11/+11
| * | | ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputsEddie Hung2020-01-171-0/+5
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* | | Merge pull request #1639 from YosysHQ/eddie/fix_read_xaigerEddie Hung2020-01-152-2/+14
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| * | | abc9: aAdd test to check $_NOT_s are absorbedEddie Hung2020-01-151-0/+12
| * | | read_aiger: $lut prefix in frontEddie Hung2020-01-151-2/+2
* | | | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_WMiodrag Milanović2020-01-151-1/+1
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| * | | synth_xilinx: fix default W value for non-xc7Eddie Hung2020-01-141-1/+1
* | | | Merge pull request #1635 from YosysHQ/eddie/print_statsEddie Hung2020-01-141-25/+13
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| * | | | As before, only display MEM if Linux or FreeBSDEddie Hung2020-01-141-3/+7
| * | | | print_stats footer to return peak memory, option for including childrenEddie Hung2020-01-141-28/+12
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* | | | Merge pull request #1633 from YosysHQ/eddie/fix_autonameEddie Hung2020-01-142-1/+20
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| * | | | autoname: do not autoname portsEddie Hung2020-01-141-1/+1
| * | | | autoname: add testcase with $-prefix-ed portEddie Hung2020-01-141-0/+19
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* | | | Merge pull request #1632 from YosysHQ/eddie/fix1630Eddie Hung2020-01-145-17/+23
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| * | | | read_aiger: also rename "$0"Eddie Hung2020-01-141-2/+2
| * | | | read_aiger: uniquify wires with $aiger<autoidx> prefixEddie Hung2020-01-132-9/+13
| * | | | Add #1630 testcaseEddie Hung2020-01-132-0/+2
| * | | | read_aiger: make $and/$not/$lut the prefix not suffixEddie Hung2020-01-132-9/+9
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* | | | Merge pull request #1623 from YosysHQ/mmicko/edif_attrMiodrag Milanović2020-01-145-35/+46
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| * | | this one is fineMiodrag Milanovic2020-01-101-3/+3
| * | | Fix testsMiodrag Milanovic2020-01-103-12/+11
| * | | remove whitespaceMiodrag Milanovic2020-01-101-1/+1
| * | | Use CARRY4 for abc1 as well, preventing issues with VivadoMiodrag Milanovic2020-01-101-1/+1
| * | | Export wire properties as well in EDIFMiodrag Milanovic2020-01-101-26/+38
* | | | Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpadEddie Hung2020-01-136-36/+147
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| * | | | Another conflictEddie Hung2020-01-111-1/+0
| * | | | MIssed this merge conflictEddie Hung2020-01-111-4/+0
| * | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpadEddie Hung2020-01-115-86/+118
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| * | | | | abc9: fix help message, found by @nakengelhardtEddie Hung2020-01-111-2/+2
| * | | | | Copy-pastaEddie Hung2020-01-101-1/+1
| * | | | | synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macroEddie Hung2020-01-101-4/+11
| * | | | | abc9: add abc9.verify and abc9.debug optionsEddie Hung2020-01-101-1/+13
| * | | | | abc9: fix typosEddie Hung2020-01-101-4/+4
| * | | | | Add abc9 sanity testEddie Hung2020-01-091-0/+40
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