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authorEddie Hung <eddie@fpgeh.com>2020-01-14 11:40:54 -0800
committerGitHub <noreply@github.com>2020-01-14 11:40:54 -0800
commit61ffd2d1996befd8c27c4f36f07567824bd7605e (patch)
treee1e2a1372e3feb25fa1b7472b020116acc8382dd
parent9fa0e03cc90548d0817346d0fcd72473b7d489ae (diff)
parentde969adcd8214592dfa32be5b61903fe7893d29b (diff)
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Merge pull request #1633 from YosysHQ/eddie/fix_autoname
autoname: do not rename ports
-rw-r--r--passes/cmds/autoname.cc2
-rw-r--r--tests/various/autoname.ys19
2 files changed, 20 insertions, 1 deletions
diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc
index 4614a8153..50632201e 100644
--- a/passes/cmds/autoname.cc
+++ b/passes/cmds/autoname.cc
@@ -56,7 +56,7 @@ int autoname_worker(Module *module)
for (auto &conn : cell->connections()) {
string suffix = stringf("_%s", log_id(conn.first));
for (auto bit : conn.second)
- if (bit.wire != nullptr && bit.wire->name[0] == '$') {
+ if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
IdString new_name(cell->name.str() + suffix);
int score = wire_score.at(bit.wire);
if (cell->output(conn.first)) score = 0;
diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys
new file mode 100644
index 000000000..830962e81
--- /dev/null
+++ b/tests/various/autoname.ys
@@ -0,0 +1,19 @@
+read_ilang <<EOT
+autoidx 2
+module \top
+ wire output 3 $y
+ wire input 1 \a
+ wire input 2 \b
+ cell $and \b_$and_B
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \a
+ connect \B \b
+ connect \Y $y
+ end
+end
+EOT
+autoname