aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
| * | | | Merge pull request #1062 from tux3/patch-1Clifford Wolf2019-06-041-1/+1
| |\ \ \ \
| | * | | | README.md: Missing formatting for <tag>Tux32019-06-041-1/+1
| |/ / / /
* | | | | Rename shregmap -tech xilinx -> xilinx_dynamicEddie Hung2019-06-042-6/+6
* | | | | Add log_assert to ensure no loopsEddie Hung2019-06-041-1/+15
* | | | | Only toposort builtin and abc typesEddie Hung2019-06-041-6/+9
* | | | | Add space between -D and _ABCEddie Hung2019-06-041-2/+2
* | | | | Add (* abc_flop_q *) to brams_bb.vEddie Hung2019-06-041-8/+8
* | | | | Fix name clashEddie Hung2019-06-041-11/+11
* | | | | Add mux_map.v for wide muxEddie Hung2019-06-044-30/+82
* | | | | Move ff_map back after ABC for shregmapEddie Hung2019-06-031-4/+4
* | | | | Respect -nocarryEddie Hung2019-06-031-1/+3
* | | | | Fix pmux2shiftx logicEddie Hung2019-06-031-1/+1
* | | | | Merge mistakeEddie Hung2019-06-031-14/+6
* | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-036-5/+40
|\| | | |
| * | | | Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_mapEddie Hung2019-06-031-6/+5
| |\ \ \ \
| | * | | | Remove extra newlineEddie Hung2019-06-031-1/+0
| | * | | | Execute techmap and arith_map simultaneouslyEddie Hung2019-06-031-6/+6
| |/ / / /
| * | | / Only support Symbiotic EDA flavored VerificClifford Wolf2019-06-021-0/+8
| | |_|/ | |/| |
| * | | Fix "tee" handling of log_streamsClifford Wolf2019-05-311-0/+5
| * | | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ...Clifford Wolf2019-05-301-0/+3
| * | | Merge pull request #1057 from mmicko/fix_478Clifford Wolf2019-05-301-0/+4
| |\ \ \
| | * | | Aded one more load of .conf to support change of prefixMiodrag Milanovic2019-05-291-0/+4
| |/ / /
| * | | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-282-4/+15
| |\ \ \
| | * | | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-282-4/+15
* | | | | TypoEddie Hung2019-06-031-1/+1
* | | | | IS_C_INVERTEDEddie Hung2019-06-031-4/+4
* | | | | Fix `ifndefEddie Hung2019-06-031-1/+1
* | | | | Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)Eddie Hung2019-06-034-8/+8
* | | | | Assert that box_unique_id is indeed uniqueEddie Hung2019-06-031-2/+3
* | | | | Remove dupeEddie Hung2019-06-031-7/+7
* | | | | Skip internal modules when generating box_unique_idEddie Hung2019-06-031-0/+1
* | | | | When creating new holes cell, inherit parameters tooEddie Hung2019-06-031-1/+3
* | | | | OoopsieEddie Hung2019-06-031-1/+1
* | | | | Consistent with xilinxEddie Hung2019-06-033-4/+4
* | | | | Add flops as blackboxesEddie Hung2019-05-312-0/+27
* | | | | Add FD*E_1 -> FD*E techmap rulesEddie Hung2019-05-311-5/+31
* | | | | Techmap flops before ABC againEddie Hung2019-05-311-4/+4
* | | | | parse_xaiger to cope with flopsEddie Hung2019-05-312-83/+123
* | | | | ABC9 to understand flopsEddie Hung2019-05-311-46/+27
* | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-05-315-15/+99
|\ \ \ \ \
| * | | | | Fix abc9 with (* keep *) wiresEddie Hung2019-04-232-6/+52
| * | | | | Move clean from aigerparse to abc9Eddie Hung2019-04-232-2/+1
| * | | | | Use nonblockingEddie Hung2019-04-231-1/+1
| * | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-228-41/+382
| |\ \ \ \ \
| | * \ \ \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-228-41/+382
| | |\ \ \ \ \
| * | | | | | | Tidy upEddie Hung2019-04-222-7/+1
| * | | | | | | Revert "Temporarily remove 'r' extension"Eddie Hung2019-04-222-7/+95
| |/ / / / / /
* | | | | | | Throw out unused code inherited from abcEddie Hung2019-05-311-212/+3
* | | | | | | Fix issue where keep signal became PI, but also box was adding CI driverEddie Hung2019-05-301-5/+19
* | | | | | | read_xaiger() to name box signalsEddie Hung2019-05-301-4/+8