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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-04 11:56:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-04 11:56:58 -0700 |
| commit | 1b836c93bbaa3c85d4730b0251aed64cdf207422 (patch) | |
| tree | ed3f087e429f911152190d6b9e860945303ccd90 | |
| parent | 82d41bc2f2460a06e153eac4f3968ef29ce5a63d (diff) | |
| download | yosys-1b836c93bbaa3c85d4730b0251aed64cdf207422.tar.gz yosys-1b836c93bbaa3c85d4730b0251aed64cdf207422.tar.bz2 yosys-1b836c93bbaa3c85d4730b0251aed64cdf207422.zip | |
Only toposort builtin and abc types
| -rw-r--r-- | backends/aiger/xaiger.cc | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 818caebba..4d45bb650 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -181,14 +181,17 @@ struct XAigerWriter for (auto cell : module->cells()) { RTLIL::Module* inst_module = module->design->module(cell->type); - bool known_type = yosys_celltypes.cell_known(cell->type); + bool builtin_type = yosys_celltypes.cell_known(cell->type); + bool abc_type = inst_module && inst_module->attributes.count("\\abc_box_id"); if (!holes_mode) { toposort.node(cell->name); - for (const auto &conn : cell->connections()) - { + for (const auto &conn : cell->connections()) { + if (!builtin_type && !abc_type) + continue; + if (!cell->type.in("$_NOT_", "$_AND_")) { - if (known_type) { + if (builtin_type) { if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA")) continue; if (cell->type == "$memrd" && conn.first == "\\DATA") @@ -199,8 +202,8 @@ struct XAigerWriter RTLIL::Wire* inst_module_port = inst_module->wire(conn.first); log_assert(inst_module_port); - if (inst_module_port->attributes.count("\\abc_flop_q")) - continue; + if (inst_module_port->port_output && inst_module_port->attributes.count("\\abc_flop_q")) + continue; } } |