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* Update abc attributes on FD*E_1Eddie Hung2019-06-051-6/+26
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* CleanupEddie Hung2019-06-052-17/+0
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* Call shregmap -tech xilinx_staticEddie Hung2019-06-051-1/+1
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* Revert "Move ff_map back after ABC for shregmap"Eddie Hung2019-06-051-4/+4
| | | | This reverts commit 9b9bd4e19f3da363eb3c90ef27ace282716d2e06.
* Add -tech xilinx_staticEddie Hung2019-06-051-2/+13
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* Refactor to ShregmapTechXilinx7StaticEddie Hung2019-06-051-46/+86
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* shregmap -tech xilinx_dynamic to work -params and -enpolEddie Hung2019-06-051-6/+26
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* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-053-28/+95
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| * Merge pull request #1066 from YosysHQ/clifford/fix1056Clifford Wolf2019-06-051-1/+0
| |\ | | | | | | Remove yosys_banner() from python wrapper init
| | * Remove yosys_banner() from python wrapper init, fixes #1056Clifford Wolf2019-06-051-1/+0
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Major rewrite of wire selection in setundef -initClifford Wolf2019-06-051-30/+89
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Indent fixClifford Wolf2019-06-051-23/+25
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #999 from jakobwenzel/setundefInitFixClifford Wolf2019-06-051-16/+23
| |\ \ | | | | | | | | initialize more registers in setundef -init
| | * | initialize more registers in setundef -initJakob Wenzel2019-05-091-16/+23
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| * | | Fix typo in fmcombine log message, fixes #1063Clifford Wolf2019-06-051-2/+2
| | |/ | |/| | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge remote-tracking branch 'origin/clifford/fix1065' into xc7muxEddie Hung2019-06-052-2/+2
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| * | | Suppress driver-driver conflict warning for unknown cell types, fixes #1065Clifford Wolf2019-06-051-1/+1
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1062 from tux3/patch-1Clifford Wolf2019-06-041-1/+1
| |\ \ | | | | | | | | README.md: Missing formatting for <tag>
| | * | README.md: Missing formatting for <tag>Tux32019-06-041-1/+1
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* | | Rename shregmap -tech xilinx -> xilinx_dynamicEddie Hung2019-06-042-6/+6
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* | | Add log_assert to ensure no loopsEddie Hung2019-06-041-1/+15
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* | | Only toposort builtin and abc typesEddie Hung2019-06-041-6/+9
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* | | Add space between -D and _ABCEddie Hung2019-06-041-2/+2
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* | | Add (* abc_flop_q *) to brams_bb.vEddie Hung2019-06-041-8/+8
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* | | Fix name clashEddie Hung2019-06-041-11/+11
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* | | Add mux_map.v for wide muxEddie Hung2019-06-044-30/+82
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* | | Move ff_map back after ABC for shregmapEddie Hung2019-06-031-4/+4
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* | | Respect -nocarryEddie Hung2019-06-031-1/+3
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* | | Fix pmux2shiftx logicEddie Hung2019-06-031-1/+1
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* | | Merge mistakeEddie Hung2019-06-031-14/+6
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-036-5/+40
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| * | Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_mapEddie Hung2019-06-031-6/+5
| |\ \ | | | | | | | | Execute techmap and arith_map simultaneously
| | * | Remove extra newlineEddie Hung2019-06-031-1/+0
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| | * | Execute techmap and arith_map simultaneouslyEddie Hung2019-06-031-6/+6
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| * | Only support Symbiotic EDA flavored VerificClifford Wolf2019-06-021-0/+8
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fix "tee" handling of log_streamsClifford Wolf2019-05-311-0/+5
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ↵Clifford Wolf2019-05-301-0/+3
| | | | | | | | | | | | | | | | | | fixes #1055 Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1057 from mmicko/fix_478Clifford Wolf2019-05-301-0/+4
| |\ \ | | | | | | | | Aded one more load of .conf to support change of prefix
| | * | Aded one more load of .conf to support change of prefixMiodrag Milanovic2019-05-291-0/+4
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| * | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-282-4/+15
| |\ \ | | | | | | | | Do not use shiftmul peepopt pattern when mul result is truncated
| | * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-282-4/+15
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | TypoEddie Hung2019-06-031-1/+1
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* | | | IS_C_INVERTEDEddie Hung2019-06-031-4/+4
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* | | | Fix `ifndefEddie Hung2019-06-031-1/+1
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* | | | Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)Eddie Hung2019-06-034-8/+8
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* | | | Assert that box_unique_id is indeed uniqueEddie Hung2019-06-031-2/+3
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* | | | Remove dupeEddie Hung2019-06-031-7/+7
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* | | | Skip internal modules when generating box_unique_idEddie Hung2019-06-031-0/+1
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* | | | When creating new holes cell, inherit parameters tooEddie Hung2019-06-031-1/+3
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* | | | OoopsieEddie Hung2019-06-031-1/+1
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