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* Merge pull request #3108 from YosysHQ/claire/verificdefsClaire Xen2021-12-131-1/+2
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| * Add YOSYS to the implicitly defined verilog macros in verificClaire Xenia Wolf2021-12-131-1/+2
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* Bump versiongithub-actions[bot]2021-12-131-1/+1
* Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-123-1/+214
* Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2Catherine2021-12-122-108/+80
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| * cxxrtl: preserve interior memory pointers across reset.Catherine2021-12-112-95/+67
| * cxxrtl: use unique_ptr<value<>[]> to store memory contents.whitequark2021-12-111-16/+16
* | Bump versiongithub-actions[bot]2021-12-121-1/+1
* | Fix unused param warning with ENABLE_NDEBUG.Marcelina Kościelnicka2021-12-121-1/+1
* | rtlil: Dump empty connections when whole module is selected.Marcelina Kościelnicka2021-12-121-2/+2
* | Merge pull request #3103 from whitequark/write_verilog-more-zero-width-valuesCatherine2021-12-111-1/+2
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| * write_verilog: dump zero width sigspecs correctly.whitequark2021-12-111-1/+2
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* Bump versiongithub-actions[bot]2021-12-111-1/+1
* Merge pull request #3102 from YosysHQ/claire/enumxzMiodrag Milanović2021-12-101-1/+1
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| * Fix verific import of enum values with x and/or zClaire Xenia Wolf2021-12-101-1/+1
* | Merge pull request #3097 from YosysHQ/modportMiodrag Milanović2021-12-101-2/+12
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| * Update verific.ccClaire Xen2021-12-101-4/+7
| * If direction NONE use that from first bitMiodrag Milanovic2021-12-081-0/+7
* | Merge pull request #3099 from YosysHQ/claire/readargsClaire Xen2021-12-109-41/+52
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| * | Fix the tests we just brokeClaire Xenia Wolf2021-12-106-10/+10
| * | Added "yosys -r <topmodule>"Claire Xenia Wolf2021-12-103-28/+35
| * | Use "read" command to parse HDL files from Yosys command-lineClaire Xenia Wolf2021-12-091-4/+8
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* | Bump versiongithub-actions[bot]2021-12-091-1/+1
* | opt_mem_priority: Fix non-ascii char in help message.Marcelina Kościelnicka2021-12-092-12/+2
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* Bump versiongithub-actions[bot]2021-12-041-1/+1
* Next dev cycleMiodrag Milanovic2021-12-032-2/+5
* Release version 0.12Miodrag Milanovic2021-12-032-3/+3
* Update manualMiodrag Milanovic2021-12-031-22/+181
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
* Make sure cell names are unique for wide operatorsMiodrag Milanovic2021-12-031-2/+2
* Bump versiongithub-actions[bot]2021-12-021-1/+1
* Update CHANGELOG and CODEOWNERSMiodrag Milanovic2021-12-012-0/+22
* Bump versiongithub-actions[bot]2021-11-261-1/+1
* intel_alm: preliminary Arria V supportLofty2021-11-256-7/+199
* sta: very crude static timing analysis passLofty2021-11-259-62/+502
* Bump versiongithub-actions[bot]2021-11-181-1/+1
* Merge pull request #3080 from YosysHQ/micko/init_wireMiodrag Milanović2021-11-171-4/+6
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| * Give initial wire unique ID, fixes #2914Miodrag Milanovic2021-11-171-4/+6
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* Bump versiongithub-actions[bot]2021-11-171-1/+1
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-162-7/+74
* Bump versiongithub-actions[bot]2021-11-141-1/+1
* synth_gatemate Revert cascade A/B port mixupPatrick Urban2021-11-132-12/+4
* synth_gatemate: Remove iob_map invokationPatrick Urban2021-11-131-1/+0
* synth_gatemate: Add block RAM cascade supportPatrick Urban2021-11-132-112/+96
* synth_gatemate: Remove obsolete iob_mapPatrick Urban2021-11-133-61/+2
* synth_gatemate: Update passPatrick Urban2021-11-132-69/+33
* synth_gatemate: Remove specify blocksPatrick Urban2021-11-131-92/+0
* synth_gatemate: Remove gatemate_bramopt passPatrick Urban2021-11-133-148/+0
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
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