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| author | Catherine <whitequark@whitequark.org> | 2021-12-11 16:24:47 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-11 16:24:47 +0000 |
| commit | 21fbdb6638bc00758dfe7aaac93c5805160168d5 (patch) | |
| tree | 6782061feabf37590b146aa194f66717160e146a | |
| parent | 8e91857fabe75e032810bb09a22af1b18cb8172f (diff) | |
| parent | 86f2804dc3f80cd74349c62888376c8596fb1856 (diff) | |
| download | yosys-21fbdb6638bc00758dfe7aaac93c5805160168d5.tar.gz yosys-21fbdb6638bc00758dfe7aaac93c5805160168d5.tar.bz2 yosys-21fbdb6638bc00758dfe7aaac93c5805160168d5.zip | |
Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values
write_verilog: dump zero width sigspecs correctly
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 47ef1c479..13c78c526 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -358,7 +358,8 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) { if (GetSize(sig) == 0) { - f << "\"\""; + // See IEEE 1364-2005 Clause 5.1.14. + f << "{0{1'b0}}"; return; } if (sig.is_chunk()) { |