diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-12-11 16:53:54 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-12-12 01:22:06 +0100 |
| commit | d019b4e6810bce37bd3477bb365288cae2a572b2 (patch) | |
| tree | 018b64ae47f1161c3da42e88a4d4113a12aa1db8 | |
| parent | 21fbdb6638bc00758dfe7aaac93c5805160168d5 (diff) | |
| download | yosys-d019b4e6810bce37bd3477bb365288cae2a572b2.tar.gz yosys-d019b4e6810bce37bd3477bb365288cae2a572b2.tar.bz2 yosys-d019b4e6810bce37bd3477bb365288cae2a572b2.zip | |
rtlil: Dump empty connections when whole module is selected.
Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires. This makes debugging rather confusing.
| -rw-r--r-- | backends/rtlil/rtlil_backend.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 68521d52d..1b11de5ec 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -358,8 +358,8 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu bool first_conn_line = true; for (auto it = module->connections().begin(); it != module->connections().end(); ++it) { - bool show_conn = !only_selected; - if (only_selected) { + bool show_conn = !only_selected || design->selected_whole_module(module->name); + if (!show_conn) { RTLIL::SigSpec sigs = it->first; sigs.append(it->second); for (auto &c : sigs.chunks()) { |