iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Revert "ABC to call retime all the time"	Eddie Hung	2019-12-30	1	-11/+15
*	Merge pull request #1599 from YosysHQ/eddie/retry_1588	Eddie Hung	2019-12-30	4	-20/+87
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\| *	Add #1598 testcase	Eddie Hung	2019-12-27	3	-0/+48
\| *	write_xaiger: inherit port ordering from original module	Eddie Hung	2019-12-27	1	-5/+16
\| *	Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"	Eddie Hung	2019-12-27	1	-19/+27
* \|	Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5	Eddie Hung	2019-12-30	3	-14/+6
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\| *	Update resource count	Eddie Hung	2019-12-28	1	-3/+3
\| *	Nitpick cleanup for ecp5	Eddie Hung	2019-12-27	2	-11/+3
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*	Merge branch 'master' of github.com:YosysHQ/yosys	Eddie Hung	2019-12-27	1	-27/+19
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\| *	Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup	David Shah	2019-12-27	1	-27/+19
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\| \| *	Revert "write_xaiger: only instantiate each whitebox cell type once"	David Shah	2019-12-27	1	-27/+19
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* /	write_xaiger: simplify c{i,o}_bits	Eddie Hung	2019-12-27	1	-12/+6
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*	fixed invalid char	Miodrag Milanovic	2019-12-25	1	-1/+1
*	iopadmap: Emit tristate buffers with const OE for some edge cases.	Marcin Kościelnicki	2019-12-25	2	-23/+91
*	Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen	Marcin Kościelnicki	2019-12-25	12	-81/+1136
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\| *	Minor nit fixes	Marcin Kościelnicki	2019-12-25	1	-2/+2
\| *	Add DSP cascade tests	Eddie Hung	2019-12-23	1	-0/+89
\| *	Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too	Eddie Hung	2019-12-23	1	-8/+18
\| *	Fix CEA/CEB check	Eddie Hung	2019-12-23	1	-2/+2
\| *	Fix checking CE[AB] and for direct connections	Eddie Hung	2019-12-23	1	-18/+40
\| *	Support unregistered cascades for A and B inputs	Eddie Hung	2019-12-23	1	-47/+74
\| *	Add DSP48A* PCOUT -> PCIN cascade support	Eddie Hung	2019-12-23	1	-10/+10
\| *	xilinx_dsp: Initial DSP48A/DSP48A1 support.	Marcin Kościelnicki	2019-12-22	10	-14/+921
* \|	xilinx: Test our DSP48A/DSP48A1 simulation models.	Marcin Kościelnicki	2019-12-23	5	-7/+362
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*	Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup	Eddie Hung	2019-12-20	1	-19/+27
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\| *	write_xaiger: only instantiate each whitebox cell type once	Eddie Hung	2019-12-20	1	-19/+27
* \|	Add abc9_arrival times for RAM{32,64}M	Eddie Hung	2019-12-20	1	-24/+10
* \|	Add RAM{32,64}M to abc9_map.v	Eddie Hung	2019-12-20	1	-0/+78
* \|	Put specify/endspecify inside ``	Eddie Hung	2019-12-20	1	-4/+4
* \|	Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut	Eddie Hung	2019-12-20	1	-19/+18
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\| *	Interpret "abc9 -lut" as lut string only if [0-9:]	Eddie Hung	2019-12-18	1	-19/+18
* \|	Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup	Eddie Hung	2019-12-20	4	-39/+21
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\| * \|	Revert "Optimise write_xaiger"	Eddie Hung	2019-12-20	4	-39/+21
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* \|	Fix linking with Python 3.8	Graham Edgecombe	2019-12-20	1	-0/+7
* \|	Add PYTHON_CONFIG variable to the Makefile	Graham Edgecombe	2019-12-20	1	-17/+18
* \|	Merge pull request #1581 from YosysHQ/clifford/fix1565	Eddie Hung	2019-12-19	1	-1/+1
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\| * \|	Fix sim for assignments with lhs<rhs size, fixes #1565	Clifford Wolf	2019-12-17	1	-1/+1
* \| \|	Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup	Eddie Hung	2019-12-19	4	-21/+39
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\| * \| \|	Stray newline	Eddie Hung	2019-12-06	1	-1/+0
\| * \| \|	write_xaiger to inst each cell type once, do not call techmap/aigmap	Eddie Hung	2019-12-06	1	-21/+25
\| * \| \|	techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger	Eddie Hung	2019-12-06	3	-0/+15
* \| \| \|	Merge pull request #1569 from YosysHQ/eddie/fix_1531	Eddie Hung	2019-12-19	2	-0/+50
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\| * \| \| \|	Stray log_dump	Eddie Hung	2019-12-11	1	-1/+0
\| * \| \| \|	Preserve size of $genval$-s in for loops	Eddie Hung	2019-12-11	1	-0/+17
\| * \| \| \|	Add testcase	Eddie Hung	2019-12-11	1	-0/+34
* \| \| \| \|	Merge pull request #1571 from YosysHQ/eddie/fix_1570	Eddie Hung	2019-12-19	1	-3/+1
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\| * \| \| \| \|	Make SV2017 compliant courtesy of @wsnyder	Eddie Hung	2019-12-12	1	-3/+1
* \| \| \| \| \|	xilinx: Add simulation models for remaining CLB primitives.	Marcin Kościelnicki	2019-12-19	3	-156/+210
* \| \| \| \| \|	xilinx_dffopt: Keep order of LUT inputs.	Marcin Kościelnicki	2019-12-19	1	-16/+30
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* \| \| \| \|	Add "scratchpad" to CHANGELOG	Eddie Hung	2019-12-18	1	-0/+1