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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 12:21:22 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-19 12:21:22 -0500 |
| commit | d675f22f4e4166ef2cd13f1a9a28f8bd35511539 (patch) | |
| tree | 2dc15b3e7555b38a926a7f4011372fa24d38b351 | |
| parent | 8b2c9f4518aa27662a29de5d282df44f1bba6dc8 (diff) | |
| parent | 23fcfd0adb51f800936b70999a5f95fe59ee7631 (diff) | |
| download | yosys-d675f22f4e4166ef2cd13f1a9a28f8bd35511539.tar.gz yosys-d675f22f4e4166ef2cd13f1a9a28f8bd35511539.tar.bz2 yosys-d675f22f4e4166ef2cd13f1a9a28f8bd35511539.zip | |
Merge pull request #1571 from YosysHQ/eddie/fix_1570
mem_arst.v: do not redeclare ANSI port
| -rw-r--r-- | tests/simple/mem_arst.v | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v index 9bd38fcb3..88d0553b9 100644 --- a/tests/simple/mem_arst.v +++ b/tests/simple/mem_arst.v @@ -7,11 +7,9 @@ module MyMem #( input Clk_i, input [AddrWidth-1:0] Addr_i, input [DataWidth-1:0] Data_i, - output [DataWidth-1:0] Data_o, + output reg [DataWidth-1:0] Data_o, input WR_i); - reg [DataWidth-1:0] Data_o; - localparam Size = 2**AddrWidth; (* mem2reg *) |