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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 12:21:33 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-19 12:21:33 -0500 |
| commit | d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c (patch) | |
| tree | 29413acb3d172859516920d054bfddcdf0fec482 | |
| parent | d675f22f4e4166ef2cd13f1a9a28f8bd35511539 (diff) | |
| parent | 1ac1697e15ff72e69f4dfbf6922f0871c81bdff2 (diff) | |
| download | yosys-d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c.tar.gz yosys-d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c.tar.bz2 yosys-d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c.zip | |
Merge pull request #1569 from YosysHQ/eddie/fix_1531
verilog: preserve size of $genval$-s in for loops
| -rw-r--r-- | frontends/ast/simplify.cc | 16 | ||||
| -rw-r--r-- | tests/various/bug1531.ys | 34 |
2 files changed, 50 insertions, 0 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 44fd32cdc..b94a8d710 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1198,6 +1198,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, varbuf = new AstNode(AST_LOCALPARAM, varbuf); varbuf->str = init_ast->children[0]->str; + auto resolved = current_scope.at(init_ast->children[0]->str); + if (resolved->range_valid) { + varbuf->range_left = resolved->range_left; + varbuf->range_right = resolved->range_right; + varbuf->range_swapped = resolved->range_swapped; + varbuf->range_valid = resolved->range_valid; + } + AstNode *backup_scope_varbuf = current_scope[varbuf->str]; current_scope[varbuf->str] = varbuf; @@ -2998,6 +3006,14 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma current_ast_mod->children.push_back(p); str = p->str; id2ast = p; + + auto resolved = current_scope.at(index_var); + if (resolved->range_valid) { + p->range_left = resolved->range_left; + p->range_right = resolved->range_right; + p->range_swapped = resolved->range_swapped; + p->range_valid = resolved->range_valid; + } } } diff --git a/tests/various/bug1531.ys b/tests/various/bug1531.ys new file mode 100644 index 000000000..542223030 --- /dev/null +++ b/tests/various/bug1531.ys @@ -0,0 +1,34 @@ +read_verilog <<EOT +module top (y, clk, w); + output reg y = 1'b0; + input clk, w; + reg [1:0] i = 2'b00; + always @(posedge clk) + // If the constant below is set to 2'b00, the correct output is generated. + // vvvv + for (i = 1'b0; i < 2'b01; i = i + 2'b01) + y <= w || i[1:1]; +endmodule +EOT + +synth +design -stash gate + +read_verilog <<EOT +module gold (y, clk, w); + input clk; + wire [1:0] i; + input w; + output y; + reg y = 1'h0; + always @(posedge clk) + y <= w; + assign i = 2'h0; +endmodule +EOT +proc gold + +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 10 -verify -prove-asserts -show-ports miter |