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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-28 02:15:11 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-28 02:15:11 -0800 |
| commit | 011f749ecfe37711552be7b9c7712931e82c3757 (patch) | |
| tree | c3f0b1c301bac3e8cc39b3903567dfacc4bf9b0f | |
| parent | 71906fab51c60d22ee5b145df0429287ab9d2d65 (diff) | |
| download | yosys-011f749ecfe37711552be7b9c7712931e82c3757.tar.gz yosys-011f749ecfe37711552be7b9c7712931e82c3757.tar.bz2 yosys-011f749ecfe37711552be7b9c7712931e82c3757.zip | |
Update resource count
| -rw-r--r-- | tests/arch/ecp5/mux.ys | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys index 92463aa32..22866832d 100644 --- a/tests/arch/ecp5/mux.ys +++ b/tests/arch/ecp5/mux.ys @@ -39,8 +39,8 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 8 t:L6MUX21 -select -assert-count 26 t:LUT4 -select -assert-count 12 t:PFUMX +select -assert-count 12 t:L6MUX21 +select -assert-count 34 t:LUT4 +select -assert-count 17 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D |