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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 12:24:27 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-19 12:24:27 -0500 |
| commit | 269ba56a6d46d1e1692d75eecbad2bc3aaf69b23 (patch) | |
| tree | b2795e76adb45af6d8a43fb0c17974047908be30 | |
| parent | df626ee7abca3446225dac9179d7e7f380774b2c (diff) | |
| parent | 41ed6ca7a5a18aa3a2ce42e76012c43fdf2de73b (diff) | |
| download | yosys-269ba56a6d46d1e1692d75eecbad2bc3aaf69b23.tar.gz yosys-269ba56a6d46d1e1692d75eecbad2bc3aaf69b23.tar.bz2 yosys-269ba56a6d46d1e1692d75eecbad2bc3aaf69b23.zip | |
Merge pull request #1581 from YosysHQ/clifford/fix1565
Fix sim for assignments with lhs<rhs size
| -rw-r--r-- | passes/sat/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 4c3022c70..d5634b26d 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -230,7 +230,7 @@ struct SimInstance bool did_something = false; sig = sigmap(sig); - log_assert(GetSize(sig) == GetSize(value)); + log_assert(GetSize(sig) <= GetSize(value)); for (int i = 0; i < GetSize(sig); i++) if (state_nets.at(sig[i]) != value[i]) { |