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Fix xilinx tests, when iopads are default
Miodrag Milanovic
2019-12-21
17
-42
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+44
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Make iopad option default for all xilinx flows
Miodrag Milanovic
2019-12-21
1
-14
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+5
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Merge pull request #1599 from YosysHQ/eddie/retry_1588
Eddie Hung
2019-12-30
4
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+87
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Add #1598 testcase
Eddie Hung
2019-12-27
3
-0
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+48
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write_xaiger: inherit port ordering from original module
Eddie Hung
2019-12-27
1
-5
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+16
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Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"
Eddie Hung
2019-12-27
1
-19
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+27
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Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5
Eddie Hung
2019-12-30
3
-14
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+6
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Update resource count
Eddie Hung
2019-12-28
1
-3
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+3
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Nitpick cleanup for ecp5
Eddie Hung
2019-12-27
2
-11
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+3
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Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung
2019-12-27
1
-27
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+19
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Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup
David Shah
2019-12-27
1
-27
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+19
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Revert "write_xaiger: only instantiate each whitebox cell type once"
David Shah
2019-12-27
1
-27
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+19
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write_xaiger: simplify c{i,o}_bits
Eddie Hung
2019-12-27
1
-12
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+6
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fixed invalid char
Miodrag Milanovic
2019-12-25
1
-1
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+1
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iopadmap: Emit tristate buffers with const OE for some edge cases.
Marcin Kościelnicki
2019-12-25
2
-23
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+91
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Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
Marcin Kościelnicki
2019-12-25
12
-81
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+1136
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Minor nit fixes
Marcin Kościelnicki
2019-12-25
1
-2
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+2
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Add DSP cascade tests
Eddie Hung
2019-12-23
1
-0
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+89
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Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
Eddie Hung
2019-12-23
1
-8
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+18
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Fix CEA/CEB check
Eddie Hung
2019-12-23
1
-2
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+2
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Fix checking CE[AB] and for direct connections
Eddie Hung
2019-12-23
1
-18
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+40
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Support unregistered cascades for A and B inputs
Eddie Hung
2019-12-23
1
-47
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+74
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Add DSP48A* PCOUT -> PCIN cascade support
Eddie Hung
2019-12-23
1
-10
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+10
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
Marcin Kościelnicki
2019-12-22
10
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+921
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xilinx: Test our DSP48A/DSP48A1 simulation models.
Marcin Kościelnicki
2019-12-23
5
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+362
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Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung
2019-12-20
1
-19
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+27
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write_xaiger: only instantiate each whitebox cell type once
Eddie Hung
2019-12-20
1
-19
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+27
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Add abc9_arrival times for RAM{32,64}M
Eddie Hung
2019-12-20
1
-24
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+10
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Add RAM{32,64}M to abc9_map.v
Eddie Hung
2019-12-20
1
-0
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+78
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Put specify/endspecify inside ``
Eddie Hung
2019-12-20
1
-4
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+4
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Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
Eddie Hung
2019-12-20
1
-19
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+18
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Interpret "abc9 -lut" as lut string only if [0-9:]
Eddie Hung
2019-12-18
1
-19
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+18
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Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup
Eddie Hung
2019-12-20
4
-39
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+21
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Revert "Optimise write_xaiger"
Eddie Hung
2019-12-20
4
-39
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+21
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Fix linking with Python 3.8
Graham Edgecombe
2019-12-20
1
-0
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+7
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Add PYTHON_CONFIG variable to the Makefile
Graham Edgecombe
2019-12-20
1
-17
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+18
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Merge pull request #1581 from YosysHQ/clifford/fix1565
Eddie Hung
2019-12-19
1
-1
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+1
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Fix sim for assignments with lhs<rhs size, fixes #1565
Clifford Wolf
2019-12-17
1
-1
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+1
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Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung
2019-12-19
4
-21
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+39
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Stray newline
Eddie Hung
2019-12-06
1
-1
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+0
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write_xaiger to inst each cell type once, do not call techmap/aigmap
Eddie Hung
2019-12-06
1
-21
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+25
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techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
Eddie Hung
2019-12-06
3
-0
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+15
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Merge pull request #1569 from YosysHQ/eddie/fix_1531
Eddie Hung
2019-12-19
2
-0
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+50
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Stray log_dump
Eddie Hung
2019-12-11
1
-1
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+0
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Preserve size of $genval$-s in for loops
Eddie Hung
2019-12-11
1
-0
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+17
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Add testcase
Eddie Hung
2019-12-11
1
-0
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+34
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Merge pull request #1571 from YosysHQ/eddie/fix_1570
Eddie Hung
2019-12-19
1
-3
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+1
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Make SV2017 compliant courtesy of @wsnyder
Eddie Hung
2019-12-12
1
-3
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+1
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xilinx: Add simulation models for remaining CLB primitives.
Marcin Kościelnicki
2019-12-19
3
-156
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+210
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xilinx_dffopt: Keep order of LUT inputs.
Marcin Kościelnicki
2019-12-19
1
-16
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+30
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