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Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
Eddie Hung
2019-06-11
1
-10
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+15
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Try way that doesn't involve creating a new wire
Eddie Hung
2019-06-11
1
-10
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+15
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Disable dist RAM boxes due to comb loop
Eddie Hung
2019-06-11
1
-2
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+2
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Remove #ifndef ABC
Eddie Hung
2019-06-11
1
-4
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+0
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Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
Eddie Hung
2019-06-10
3
-3
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+59
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If d_bit already in sigbit_chain_next, create extra wire
Eddie Hung
2019-06-10
1
-3
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+6
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Add test
Eddie Hung
2019-06-10
2
-0
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+53
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Revert "Revert "Move ff_map back after ABC for shregmap""
Eddie Hung
2019-06-10
1
-5
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+5
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Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
Eddie Hung
2019-06-10
2
-6
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+6
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Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"
Eddie Hung
2019-06-10
1
-26
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+6
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Revert "Refactor to ShregmapTechXilinx7Static"
Eddie Hung
2019-06-10
1
-86
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+46
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Revert "Add -tech xilinx_static"
Eddie Hung
2019-06-10
1
-13
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+2
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Revert "Continue support for ShregmapTechXilinx7Static"
Eddie Hung
2019-06-10
1
-81
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+30
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Revert "shregmap -tech xilinx_static to handle INIT"
Eddie Hung
2019-06-10
1
-32
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+22
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-10
2
-1
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+30
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Add some more comments
Eddie Hung
2019-06-10
1
-1
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+6
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Merge pull request #1082 from corecode/u4k
David Shah
2019-06-10
1
-0
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+24
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ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
Simon Schubert
2019-06-10
1
-0
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+24
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Merge pull request #1078 from YosysHQ/eddie/muxcover_costs
Clifford Wolf
2019-06-08
1
-12
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+42
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Allow muxcover costs to be changed
Eddie Hung
2019-06-07
1
-12
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+42
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Update CHANGELOG
Eddie Hung
2019-06-07
1
-4
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+2
*
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Comment out muxpack (currently broken)
Eddie Hung
2019-06-07
1
-2
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+2
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Fine tune aigerparse
Eddie Hung
2019-06-07
2
-63
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+32
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-07
39
-867
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+1079
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Fix spacing from spaces to tabs
Eddie Hung
2019-06-07
1
-362
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+362
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Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger
Clifford Wolf
2019-06-07
27
-45
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+128
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Add read_aiger to CHANGELOG
Eddie Hung
2019-06-07
1
-0
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+1
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Fix spacing (entire file is wrong anyway, will fix later)
Eddie Hung
2019-06-07
1
-3
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+3
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Remove unnecessary std::getline() for ASCII
Eddie Hung
2019-06-07
1
-3
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+0
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Test *.aag too, by using *.aig as reference
Eddie Hung
2019-06-07
1
-0
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+19
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Fix read_aiger -- create zero driver, fix init width, parse 'b'
Eddie Hung
2019-06-07
2
-13
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+52
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Use ABC to convert from AIGER to Verilog
Eddie Hung
2019-06-07
1
-2
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+3
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Use ABC to convert AIGER to Verilog, then sat against Yosys
Eddie Hung
2019-06-07
1
-21
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+15
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Add symbols to AIGER test inputs for ABC
Eddie Hung
2019-06-07
22
-8
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+40
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Merge pull request #1077 from YosysHQ/clifford/pr983
Clifford Wolf
2019-06-07
9
-3
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+93
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Fixes and cleanups in AST_TECALL handling
Clifford Wolf
2019-06-07
4
-50
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+38
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Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...
Clifford Wolf
2019-06-07
10
-5
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+107
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Initial implementation of elaboration system tasks
Udi Finkelstein
2019-05-03
10
-5
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+107
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Rename implicit_ports.sv test to implicit_ports.v
Clifford Wolf
2019-06-07
1
-0
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+0
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Merge branch 'tux3-implicit_named_connection'
Clifford Wolf
2019-06-07
4
-3
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+40
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Cleanup tux3-implicit_named_connection
Clifford Wolf
2019-06-07
3
-13
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+2
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Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...
Clifford Wolf
2019-06-07
5
-4
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+52
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SystemVerilog support for implicit named port connections
tux3
2019-06-06
5
-12
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+59
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Merge pull request #1076 from thasti/centos7-build-fix
Clifford Wolf
2019-06-07
1
-1
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+0
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remove boost/log/exceptions.hpp from wrapper generator
Stefan Biereigel
2019-06-07
1
-1
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+0
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Allow muxcover costs to be changed
Eddie Hung
2019-06-07
1
-12
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+42
*
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$__XILINX_MUX_ -> $__XILINX_SHIFTX
Eddie Hung
2019-06-06
2
-11
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+11
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Fix muxcover and its techmapping
Eddie Hung
2019-06-06
2
-3
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+3
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Run muxpack and muxcover in synth_xilinx
Eddie Hung
2019-06-06
2
-1
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+18
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Remove abc_flop attributes for now
Eddie Hung
2019-06-06
1
-56
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+10
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