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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 13:12:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 13:12:48 -0700 |
| commit | f48c6920b7aa777c0c569f444e3db88211835cec (patch) | |
| tree | 17db4d2fd97197eb80dc5d2433e39be8f637fafd | |
| parent | 6934f4bdd53cb226d0c8631eff691d9a96aebbce (diff) | |
| download | yosys-f48c6920b7aa777c0c569f444e3db88211835cec.tar.gz yosys-f48c6920b7aa777c0c569f444e3db88211835cec.tar.bz2 yosys-f48c6920b7aa777c0c569f444e3db88211835cec.zip | |
Add read_aiger to CHANGELOG
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "read_aiger" frontend - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" |