Merge remote-tracking branch 'origin/master' into xc7mux

39 files changed, 1079 insertions, 867 deletions

diff --git a/CHANGELOG b/CHANGELOG
index e67d9c903..149443c74 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,7 +16,11 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
+<<<<<<< HEAD
     - Added "muxpack" pass
+=======
+    - Added "read_aiger" frontend
+>>>>>>> origin/master
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 
 
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 95335a029..20b43c3d3 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -36,881 +36,916 @@
 YOSYS_NAMESPACE_BEGIN
 
 AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
-    : design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
+	: design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
 {
-    module = new RTLIL::Module;
-    module->name = module_name;
-    if (design->module(module->name))
-        log_error("Duplicate definition of module %s!\n", log_id(module->name));
+	module = new RTLIL::Module;
+	module->name = module_name;
+	if (design->module(module->name))
+		log_error("Duplicate definition of module %s!\n", log_id(module->name));
 }
 
 void AigerReader::parse_aiger()
 {
-    std::string header;
-    f >> header;
-    if (header != "aag" && header != "aig")
-        log_error("Unsupported AIGER file!\n");
-
-    // Parse rest of header
-    if (!(f >> M >> I >> L >> O >> A))
-        log_error("Invalid AIGER header\n");
-
-    // Optional values
-    B = C = J = F = 0;
-    if (f.peek() != ' ') goto end_of_header;
-    if (!(f >> B)) log_error("Invalid AIGER header\n");
-    if (f.peek() != ' ') goto end_of_header;
-    if (!(f >> C)) log_error("Invalid AIGER header\n");
-    if (f.peek() != ' ') goto end_of_header;
-    if (!(f >> J)) log_error("Invalid AIGER header\n");
-    if (f.peek() != ' ') goto end_of_header;
-    if (!(f >> F)) log_error("Invalid AIGER header\n");
+	std::string header;
+	f >> header;
+	if (header != "aag" && header != "aig")
+		log_error("Unsupported AIGER file!\n");
+
+	// Parse rest of header
+	if (!(f >> M >> I >> L >> O >> A))
+		log_error("Invalid AIGER header\n");
+
+	// Optional values
+	B = C = J = F = 0;
+	if (f.peek() != ' ') goto end_of_header;
+	if (!(f >> B)) log_error("Invalid AIGER header\n");
+	if (f.peek() != ' ') goto end_of_header;
+	if (!(f >> C)) log_error("Invalid AIGER header\n");
+	if (f.peek() != ' ') goto end_of_header;
+	if (!(f >> J)) log_error("Invalid AIGER header\n");
+	if (f.peek() != ' ') goto end_of_header;
+	if (!(f >> F)) log_error("Invalid AIGER header\n");
 end_of_header:
 
-    std::string line;
-    std::getline(f, line); // Ignore up to start of next line, as standard
-                           // says anything that follows could be used for
-                           // optional sections
-
-    log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
-
-    line_count = 1;
-    piNum = 0;
-    flopNum = 0;
-
-    if (header == "aag")
-        parse_aiger_ascii();
-    else if (header == "aig")
-        parse_aiger_binary();
-    else
-        log_abort();
-
-    // Parse footer (symbol table, comments, etc.)
-    unsigned l1;
-    std::string s;
-    for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
-        if (c == 'i' || c == 'l' || c == 'o') {
-            f.ignore(1);
-            if (!(f >> l1 >> s))
-                log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
-
-            if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
-                log_error("Line %u has invalid symbol position!\n", line_count);
-
-            RTLIL::Wire* wire;
-            if (c == 'i') wire = inputs[l1];
-            else if (c == 'l') wire = latches[l1];
-            else if (c == 'o') wire = outputs[l1];
-            else log_abort();
-
-            module->rename(wire, stringf("\\%s", s.c_str()));
-        }
-        else if (c == 'b' || c == 'j' || c == 'f') {
-            // TODO
-        }
-        else if (c == 'c') {
-            f.ignore(1);
-            if (f.peek() == '\n')
-                break;
-            // Else constraint (TODO)
-        }
-        else
-            log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
-        std::getline(f, line); // Ignore up to start of next line
-    }
-
-    post_process();
+	std::string line;
+	std::getline(f, line); // Ignore up to start of next line, as standard
+	// says anything that follows could be used for
+	// optional sections
+
+	log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
+
+	line_count = 1;
+	piNum = 0;
+	flopNum = 0;
+
+	if (header == "aag")
+		parse_aiger_ascii();
+	else if (header == "aig")
+		parse_aiger_binary();
+	else
+		log_abort();
+
+	RTLIL::Wire* n0 = module->wire("\\n0");
+	if (n0)
+		module->connect(n0, RTLIL::S0);
+
+	for (unsigned i = 0; i < outputs.size(); ++i) {
+		RTLIL::Wire *wire = outputs[i];
+		if (wire->port_input) {
+			RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o");
+			o_wire->port_output = true;
+			wire->port_output = false;
+			module->connect(o_wire, wire);
+			outputs[i] = o_wire;
+		}
+	}
+
+	// Parse footer (symbol table, comments, etc.)
+	unsigned l1;
+	std::string s;
+	for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
+		if (c == 'i' || c == 'l' || c == 'o' || c == 'b') {
+			f.ignore(1);
+			if (!(f >> l1 >> s))
+				log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
+
+			if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
+				log_error("Line %u has invalid symbol position!\n", line_count);
+
+			RTLIL::Wire* wire;
+			if (c == 'i') wire = inputs[l1];
+			else if (c == 'l') wire = latches[l1];
+			else if (c == 'o') wire = outputs[l1];
+			else if (c == 'b') wire = bad_properties[l1];
+			else log_abort();
+
+			module->rename(wire, stringf("\\%s", s.c_str()));
+		}
+		else if (c == 'j' || c == 'f') {
+			// TODO
+		}
+		else if (c == 'c') {
+			f.ignore(1);
+			if (f.peek() == '\n')
+				break;
+			// Else constraint (TODO)
+		}
+		else
+			log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
+		std::getline(f, line); // Ignore up to start of next line
+	}
+
+	post_process();
 }
 
 static uint32_t parse_xaiger_literal(std::istream &f)
 {
-    uint32_t l;
-    f.read(reinterpret_cast<char*>(&l), sizeof(l));
-    if (f.gcount() != sizeof(l))
-        log_error("Offset %ld: unable to read literal!\n", static_cast<int64_t>(f.tellg()));
-    // TODO: Don't assume we're on little endian
+	uint32_t l;
+	f.read(reinterpret_cast<char*>(&l), sizeof(l));
+	if (f.gcount() != sizeof(l))
+		log_error("Offset %ld: unable to read literal!\n", static_cast<int64_t>(f.tellg()));
+	// TODO: Don't assume we're on little endian
 #ifdef _WIN32
-    return _byteswap_ulong(l);
+	return _byteswap_ulong(l);
 #else
-    return __builtin_bswap32(l);
+	return __builtin_bswap32(l);
 #endif
 }
 
 static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
 {
-    const unsigned variable = literal >> 1;
-    const bool invert = literal & 1;
-    RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
-    RTLIL::Wire *wire = module->wire(wire_name);
-    if (wire) return wire;
-    log_debug("Creating %s\n", wire_name.c_str());
-    wire = module->addWire(wire_name);
-    wire->port_input = wire->port_output = false;
-    if (!invert) return wire;
-    RTLIL::IdString wire_inv_name(stringf("\\__%d__", variable));
-    RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
-    if (wire_inv) {
-        if (module->cell(wire_inv_name)) return wire;
-    }
-    else {
-        log_debug("Creating %s\n", wire_inv_name.c_str());
-        wire_inv = module->addWire(wire_inv_name);
-        wire_inv->port_input = wire_inv->port_output = false;
-    }
-
-    log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
-    module->addNotGate(stringf("\\__%d__$not", variable), wire_inv, wire); // FIXME: is "$not" the right suffix?
-
-    return wire;
+	const unsigned variable = literal >> 1;
+	const bool invert = literal & 1;
+	RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
+	RTLIL::Wire *wire = module->wire(wire_name);
+	if (wire) return wire;
+	log_debug("Creating %s\n", wire_name.c_str());
+	wire = module->addWire(wire_name);
+	wire->port_input = wire->port_output = false;
+	if (!invert) return wire;
+	RTLIL::IdString wire_inv_name(stringf("\\__%d__", variable));
+	RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
+	if (wire_inv) {
+		if (module->cell(wire_inv_name)) return wire;
+	}
+	else {
+		log_debug("Creating %s\n", wire_inv_name.c_str());
+		wire_inv = module->addWire(wire_inv_name);
+		wire_inv->port_input = wire_inv->port_output = false;
+	}
+
+	log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
+	module->addNotGate(stringf("\\__%d__$not", variable), wire_inv, wire); // FIXME: is "$not" the right suffix?
+
+	return wire;
 }
 
 void AigerReader::parse_xaiger()
 {
-    std::string header;
-    f >> header;
-    if (header != "aag" && header != "aig")
-        log_error("Unsupported AIGER file!\n");
-
-    // Parse rest of header
-    if (!(f >> M >> I >> L >> O >> A))
-        log_error("Invalid AIGER header\n");
-
-    // Optional values
-    B = C = J = F = 0;
-
-    std::string line;
-    std::getline(f, line); // Ignore up to start of next line, as standard
-                           // says anything that follows could be used for
-                           // optional sections
-
-    log_debug("M=%u I=%u L=%u O=%u A=%u\n", M, I, L, O, A);
-
-    line_count = 1;
-    piNum = 0;
-    flopNum = 0;
-
-    if (header == "aag")
-        parse_aiger_ascii();
-    else if (header == "aig")
-        parse_aiger_binary();
-    else
-        log_abort();
-
-    dict<int,IdString> box_lookup;
-    for (auto m : design->modules()) {
-        auto it = m->attributes.find("\\abc_box_id");
-        if (it == m->attributes.end())
-            continue;
-        if (m->name[0] == '$') continue;
-        auto r = box_lookup.insert(std::make_pair(it->second.as_int(), m->name));
-        log_assert(r.second);
-    }
-
-    // Parse footer (symbol table, comments, etc.)
-    std::string s;
-    bool comment_seen = false;
-    for (int c = f.peek(); c != EOF; c = f.peek()) {
-        if (comment_seen || c == 'c') {
-            if (!comment_seen) {
-                f.ignore(1);
-                c = f.peek();
-                comment_seen = true;
-            }
-            if (c == '\n')
-                break;
-            f.ignore(1);
-            // XAIGER extensions
-            if (c == 'm') {
-                uint32_t dataSize = parse_xaiger_literal(f);
-                uint32_t lutNum = parse_xaiger_literal(f);
-                uint32_t lutSize = parse_xaiger_literal(f);
-                log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
-                ConstEval ce(module);
-                for (unsigned i = 0; i < lutNum; ++i) {
-                    uint32_t rootNodeID = parse_xaiger_literal(f);
-                    uint32_t cutLeavesM = parse_xaiger_literal(f);
-                    log_debug("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
-                    RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID));
-                    uint32_t nodeID;
-                    RTLIL::SigSpec input_sig;
-                    for (unsigned j = 0; j < cutLeavesM; ++j) {
-                        nodeID = parse_xaiger_literal(f);
-                        log_debug("\t%u\n", nodeID);
-                        RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID));
-                        log_assert(wire);
-                        input_sig.append(wire);
-                    }
-                    RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
-                    for (int j = 0; j < (1 << cutLeavesM); ++j) {
-                        ce.push();
-                        ce.set(input_sig, RTLIL::Const{j, static_cast<int>(cutLeavesM)});
-                        RTLIL::SigSpec o(output_sig);
-                        ce.eval(o);
-                        lut_mask[j] = o.as_const()[0];
-                        ce.pop();
-                    }
-                    RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID));
-                    log_assert(output_cell);
-                    module->remove(output_cell);
-                    module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
-                }
-            }
-            else if (c == 'r') {
-                uint32_t dataSize = parse_xaiger_literal(f);
-                flopNum = parse_xaiger_literal(f);
-                log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
-                f.ignore(flopNum * sizeof(uint32_t));
-            }
-            else if (c == 'n') {
-               parse_xaiger_literal(f);
-               f >> s;
-               log_debug("n: '%s'\n", s.c_str());
-            }
-            else if (c == 'h') {
-                f.ignore(sizeof(uint32_t));
-                uint32_t version = parse_xaiger_literal(f);
-                log_assert(version == 1);
-                uint32_t ciNum = parse_xaiger_literal(f);
-                log_debug("ciNum = %u\n", ciNum);
-                uint32_t coNum = parse_xaiger_literal(f);
-                log_debug("coNum = %u\n", coNum);
-                piNum = parse_xaiger_literal(f);
-                log_debug("piNum = %u\n", piNum);
-                uint32_t poNum = parse_xaiger_literal(f);
-                log_debug("poNum = %u\n", poNum);
-                uint32_t boxNum = parse_xaiger_literal(f);
-                log_debug("boxNum = %u\n", poNum);
-                for (unsigned i = 0; i < boxNum; i++) {
-                    f.ignore(2*sizeof(uint32_t));
-                    uint32_t boxUniqueId = parse_xaiger_literal(f);
-                    log_assert(boxUniqueId > 0);
-                    uint32_t oldBoxNum = parse_xaiger_literal(f);
-                    RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId));
-                    boxes.emplace_back(cell);
-                }
-            }
-            else if (c == 'a' || c == 'i' || c == 'o') {
-                uint32_t dataSize = parse_xaiger_literal(f);
-                f.ignore(dataSize);
-            }
-            else {
-                break;
-            }
-        }
-        else
-            log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
-    }
-
-    post_process();
+	std::string header;
+	f >> header;
+	if (header != "aag" && header != "aig")
+		log_error("Unsupported AIGER file!\n");
+
+	// Parse rest of header
+	if (!(f >> M >> I >> L >> O >> A))
+		log_error("Invalid AIGER header\n");
+
+	// Optional values
+	B = C = J = F = 0;
+
+	std::string line;
+	std::getline(f, line); // Ignore up to start of next line, as standard
+	// says anything that follows could be used for
+	// optional sections
+
+	log_debug("M=%u I=%u L=%u O=%u A=%u\n", M, I, L, O, A);
+
+	line_count = 1;
+	piNum = 0;
+	flopNum = 0;
+
+	if (header == "aag")
+		parse_aiger_ascii();
+	else if (header == "aig")
+		parse_aiger_binary();
+	else
+		log_abort();
+
+	dict<int,IdString> box_lookup;
+	for (auto m : design->modules()) {
+		auto it = m->attributes.find("\\abc_box_id");
+		if (it == m->attributes.end())
+			continue;
+		if (m->name[0] == '$') continue;
+		auto r = box_lookup.insert(std::make_pair(it->second.as_int(), m->name));
+		log_assert(r.second);
+	}
+
+	// Parse footer (symbol table, comments, etc.)
+	std::string s;
+	bool comment_seen = false;
+	for (int c = f.peek(); c != EOF; c = f.peek()) {
+		if (comment_seen || c == 'c') {
+			if (!comment_seen) {
+				f.ignore(1);
+				c = f.peek();
+				comment_seen = true;
+			}
+			if (c == '\n')
+				break;
+			f.ignore(1);
+			// XAIGER extensions
+			if (c == 'm') {
+				uint32_t dataSize = parse_xaiger_literal(f);
+				uint32_t lutNum = parse_xaiger_literal(f);
+				uint32_t lutSize = parse_xaiger_literal(f);
+				log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
+				ConstEval ce(module);
+				for (unsigned i = 0; i < lutNum; ++i) {
+					uint32_t rootNodeID = parse_xaiger_literal(f);
+					uint32_t cutLeavesM = parse_xaiger_literal(f);
+					log_debug("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
+					RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID));
+					uint32_t nodeID;
+					RTLIL::SigSpec input_sig;
+					for (unsigned j = 0; j < cutLeavesM; ++j) {
+						nodeID = parse_xaiger_literal(f);
+						log_debug("\t%u\n", nodeID);
+						RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID));
+						log_assert(wire);
+						input_sig.append(wire);
+					}
+					RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
+					for (int j = 0; j < (1 << cutLeavesM); ++j) {
+						ce.push();
+						ce.set(input_sig, RTLIL::Const{j, static_cast<int>(cutLeavesM)});
+						RTLIL::SigSpec o(output_sig);
+						ce.eval(o);
+						lut_mask[j] = o.as_const()[0];
+						ce.pop();
+					}
+					RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID));
+					log_assert(output_cell);
+					module->remove(output_cell);
+					module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
+				}
+			}
+			else if (c == 'r') {
+				uint32_t dataSize = parse_xaiger_literal(f);
+				flopNum = parse_xaiger_literal(f);
+				log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
+				f.ignore(flopNum * sizeof(uint32_t));
+			}
+			else if (c == 'n') {
+				parse_xaiger_literal(f);
+				f >> s;
+				log_debug("n: '%s'\n", s.c_str());
+			}
+			else if (c == 'h') {
+				f.ignore(sizeof(uint32_t));
+				uint32_t version = parse_xaiger_literal(f);
+				log_assert(version == 1);
+				uint32_t ciNum = parse_xaiger_literal(f);
+				log_debug("ciNum = %u\n", ciNum);
+				uint32_t coNum = parse_xaiger_literal(f);
+				log_debug("coNum = %u\n", coNum);
+				piNum = parse_xaiger_literal(f);
+				log_debug("piNum = %u\n", piNum);
+				uint32_t poNum = parse_xaiger_literal(f);
+				log_debug("poNum = %u\n", poNum);
+				uint32_t boxNum = parse_xaiger_literal(f);
+				log_debug("boxNum = %u\n", poNum);
+				for (unsigned i = 0; i < boxNum; i++) {
+					f.ignore(2*sizeof(uint32_t));
+					uint32_t boxUniqueId = parse_xaiger_literal(f);
+					log_assert(boxUniqueId > 0);
+					uint32_t oldBoxNum = parse_xaiger_literal(f);
+					RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId));
+					boxes.emplace_back(cell);
+				}
+			}
+			else if (c == 'a' || c == 'i' || c == 'o') {
+				uint32_t dataSize = parse_xaiger_literal(f);
+				f.ignore(dataSize);
+			}
+			else {
+				break;
+			}
+		}
+		else
+			log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
+	}
+
+	post_process();
 }
 
 void AigerReader::parse_aiger_ascii()
 {
-    std::string line;
-    std::stringstream ss;
-
-    unsigned l1, l2, l3;
-
-    // Parse inputs
-    for (unsigned i = 0; i < I; ++i, ++line_count) {
-        if (!(f >> l1))
-            log_error("Line %u cannot be interpreted as an input!\n", line_count);
-        log_debug("%d is an input\n", l1);
-        log_assert(!(l1 & 1)); // Inputs can't be inverted
-        RTLIL::Wire *wire = createWireIfNotExists(module, l1);
-        wire->port_input = true;
-        inputs.push_back(wire);
-    }
-
-    // Parse latches
-    RTLIL::Wire *clk_wire = nullptr;
-    if (L > 0) {
-        log_assert(clk_name != "");
-        clk_wire = module->wire(clk_name);
-        log_assert(!clk_wire);
-        log_debug("Creating %s\n", clk_name.c_str());
-        clk_wire = module->addWire(clk_name);
-        clk_wire->port_input = true;
-        clk_wire->port_output = false;
-    }
-    for (unsigned i = 0; i < L; ++i, ++line_count) {
-        if (!(f >> l1 >> l2))
-            log_error("Line %u cannot be interpreted as a latch!\n", line_count);
-        log_debug("%d %d is a latch\n", l1, l2);
-        log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
-        RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
-        RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
-
-        module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
-
-        // Reset logic is optional in AIGER 1.9
-        if (f.peek() == ' ') {
-            if (!(f >> l3))
-                log_error("Line %u cannot be interpreted as a latch!\n", line_count);
-
-            if (l3 == 0 || l3 == 1)
-                q_wire->attributes["\\init"] = RTLIL::Const(l3);
-            else if (l3 == l1) {
-                //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
-            }
-            else
-                log_error("Line %u has invalid reset literal for latch!\n", line_count);
-        }
-        else {
-            // AIGER latches are assumed to be initialized to zero
-            q_wire->attributes["\\init"] = RTLIL::Const(0);
-        }
-        latches.push_back(q_wire);
-    }
-
-    // Parse outputs
-    for (unsigned i = 0; i < O; ++i, ++line_count) {
-        if (!(f >> l1))
-            log_error("Line %u cannot be interpreted as an output!\n", line_count);
-
-        RTLIL::Wire *wire;
-        if (l1 == 0 || l1 == 1) {
-            wire = module->addWire(NEW_ID);
-            if (l1 == 0)
-                module->connect(wire, RTLIL::State::S0);
-            else if (l1 == 1)
-                module->connect(wire, RTLIL::State::S1);
-            else
-                log_abort();
-        }
-        else {
-            log_debug("%d is an output\n", l1);
-            const unsigned variable = l1 >> 1;
-            const bool invert = l1 & 1;
-            RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
-            wire = module->wire(wire_name);
-            if (!wire)
-                wire = createWireIfNotExists(module, l1);
-            else {
-                if (wire->port_input || wire->port_output) {
-                    RTLIL::Wire *new_wire = module->addWire(NEW_ID);
-                    module->connect(new_wire, wire);
-                    wire = new_wire;
-                }
-            }
-        }
-        wire->port_output = true;
-        outputs.push_back(wire);
-    }
-    std::getline(f, line); // Ignore up to start of next line
-
-    // TODO: Parse bad state properties
-    for (unsigned i = 0; i < B; ++i, ++line_count)
-        std::getline(f, line); // Ignore up to start of next line
-
-    // TODO: Parse invariant constraints
-    for (unsigned i = 0; i < C; ++i, ++line_count)
-        std::getline(f, line); // Ignore up to start of next line
-
-    // TODO: Parse justice properties
-    for (unsigned i = 0; i < J; ++i, ++line_count)
-        std::getline(f, line); // Ignore up to start of next line
-
-    // TODO: Parse fairness constraints
-    for (unsigned i = 0; i < F; ++i, ++line_count)
-        std::getline(f, line); // Ignore up to start of next line
-
-    // Parse AND
-    for (unsigned i = 0; i < A; ++i) {
-        if (!(f >> l1 >> l2 >> l3))
-            log_error("Line %u cannot be interpreted as an AND!\n", line_count);
-
-        log_debug("%d %d %d is an AND\n", l1, l2, l3);
-        log_assert(!(l1 & 1));
-        RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
-        RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
-        RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
-        module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
-    }
-    std::getline(f, line); // Ignore up to start of next line
+	std::string line;
+	std::stringstream ss;
+
+	unsigned l1, l2, l3;
+
+	// Parse inputs
+	for (unsigned i = 1; i <= I; ++i, ++line_count) {
+		if (!(f >> l1))
+			log_error("Line %u cannot be interpreted as an input!\n", line_count);
+		log_debug("%d is an input\n", l1);
+		log_assert(!(l1 & 1)); // Inputs can't be inverted
+		RTLIL::Wire *wire = createWireIfNotExists(module, l1);
+		wire->port_input = true;
+		inputs.push_back(wire);
+	}
+
+	// Parse latches
+	RTLIL::Wire *clk_wire = nullptr;
+	if (L > 0) {
+		log_assert(clk_name != "");
+		clk_wire = module->wire(clk_name);
+		log_assert(!clk_wire);
+		log_debug("Creating %s\n", clk_name.c_str());
+		clk_wire = module->addWire(clk_name);
+		clk_wire->port_input = true;
+		clk_wire->port_output = false;
+	}
+	for (unsigned i = 0; i < L; ++i, ++line_count) {
+		if (!(f >> l1 >> l2))
+			log_error("Line %u cannot be interpreted as a latch!\n", line_count);
+		log_debug("%d %d is a latch\n", l1, l2);
+		log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
+		RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
+		RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
+
+		module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
+
+		// Reset logic is optional in AIGER 1.9
+		if (f.peek() == ' ') {
+			if (!(f >> l3))
+				log_error("Line %u cannot be interpreted as a latch!\n", line_count);
+
+			if (l3 == 0)
+				q_wire->attributes["\\init"] = RTLIL::S0;
+			else if (l3 == 1)
+				q_wire->attributes["\\init"] = RTLIL::S1;
+			else if (l3 == l1) {
+				//q_wire->attributes["\\init"] = RTLIL::Sx;
+			}
+			else
+				log_error("Line %u has invalid reset literal for latch!\n", line_count);
+		}
+		else {
+			// AIGER latches are assumed to be initialized to zero
+			q_wire->attributes["\\init"] = RTLIL::S0;
+		}
+		latches.push_back(q_wire);
+	}
+
+	// Parse outputs
+	for (unsigned i = 0; i < O; ++i, ++line_count) {
+		if (!(f >> l1))
+			log_error("Line %u cannot be interpreted as an output!\n", line_count);
+
+		RTLIL::Wire *wire;
+		if (l1 == 0 || l1 == 1) {
+			wire = module->addWire(NEW_ID);
+			if (l1 == 0)
+				module->connect(wire, RTLIL::State::S0);
+			else if (l1 == 1)
+				module->connect(wire, RTLIL::State::S1);
+			else
+				log_abort();
+		}
+		else {
+			log_debug("%d is an output\n", l1);
+			const unsigned variable = l1 >> 1;
+			const bool invert = l1 & 1;
+			RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
+			wire = module->wire(wire_name);
+			if (!wire)
+				wire = createWireIfNotExists(module, l1);
+			else {
+				if (wire->port_input || wire->port_output) {
+					RTLIL::Wire *new_wire = module->addWire(NEW_ID);
+					module->connect(new_wire, wire);
+					wire = new_wire;
+				}
+			}
+		}
+		wire->port_output = true;
+		outputs.push_back(wire);
+	}
+
+	// Parse bad properties
+	for (unsigned i = 0; i < B; ++i, ++line_count) {
+		if (!(f >> l1))
+			log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
+
+		log_debug("%d is a bad state property\n", l1);
+		RTLIL::Wire *wire = createWireIfNotExists(module, l1);
+		wire->port_output = true;
+		bad_properties.push_back(wire);
+	}
+
+	// TODO: Parse invariant constraints
+	for (unsigned i = 0; i < C; ++i, ++line_count)
+		std::getline(f, line); // Ignore up to start of next line
+
+	// TODO: Parse justice properties
+	for (unsigned i = 0; i < J; ++i, ++line_count)
+		std::getline(f, line); // Ignore up to start of next line
+
+	// TODO: Parse fairness constraints
+	for (unsigned i = 0; i < F; ++i, ++line_count)
+		std::getline(f, line); // Ignore up to start of next line
+
+	// Parse AND
+	for (unsigned i = 0; i < A; ++i) {
+		if (!(f >> l1 >> l2 >> l3))
+			log_error("Line %u cannot be interpreted as an AND!\n", line_count);
+
+		log_debug("%d %d %d is an AND\n", l1, l2, l3);
+		log_assert(!(l1 & 1));
+		RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
+		RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
+		RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
+		module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
+	}
+	std::getline(f, line); // Ignore up to start of next line
 }
 
 static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
 {
-    unsigned x = 0, i = 0;
-    unsigned char ch;
-    while ((ch = f.get()) & 0x80)
-        x |= (ch & 0x7f) << (7 * i++);
-    return ref - (x | (ch << (7 * i)));
+	unsigned x = 0, i = 0;
+	unsigned char ch;
+	while ((ch = f.get()) & 0x80)
+		x |= (ch & 0x7f) << (7 * i++);
+	return ref - (x | (ch << (7 * i)));
 }
 
 void AigerReader::parse_aiger_binary()
 {
-    unsigned l1, l2, l3;
-    std::string line;
-
-    // Parse inputs
-    for (unsigned i = 1; i <= I; ++i) {
-        log_debug("%d is an input\n", i);
-        RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
-        wire->port_input = true;
-        log_assert(!wire->port_output);
-        inputs.push_back(wire);
-    }
-
-    // Parse latches
-    RTLIL::Wire *clk_wire = nullptr;
-    if (L > 0) {
-        log_assert(clk_name != "");
-        clk_wire = module->wire(clk_name);
-        log_assert(!clk_wire);
-        log_debug("Creating %s\n", clk_name.c_str());
-        clk_wire = module->addWire(clk_name);
-        clk_wire->port_input = true;
-        clk_wire->port_output = false;
-    }
-    l1 = (I+1) * 2;
-    for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
-        if (!(f >> l2))
-            log_error("Line %u cannot be interpreted as a latch!\n", line_count);
-        log_debug("%d %d is a latch\n", l1, l2);
-        RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
-        RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
-
-        module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
-
-        // Reset logic is optional in AIGER 1.9
-        if (f.peek() == ' ') {
-            if (!(f >> l3))
-                log_error("Line %u cannot be interpreted as a latch!\n", line_count);
-
-            if (l3 == 0 || l3 == 1)
-                q_wire->attributes["\\init"] = RTLIL::Const(l3);
-            else if (l3 == l1) {
-                //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
-            }
-            else
-                log_error("Line %u has invalid reset literal for latch!\n", line_count);
-        }
-        else {
-            // AIGER latches are assumed to be initialized to zero
-            q_wire->attributes["\\init"] = RTLIL::Const(0);
-        }
-        latches.push_back(q_wire);
-    }
-
-    // Parse outputs
-    for (unsigned i = 0; i < O; ++i, ++line_count) {
-        if (!(f >> l1))
-            log_error("Line %u cannot be interpreted as an output!\n", line_count);
-
-        RTLIL::Wire *wire;
-        if (l1 == 0 || l1 == 1) {
-            wire = module->addWire(NEW_ID);
-            if (l1 == 0)
-                module->connect(wire, RTLIL::State::S0);
-            else if (l1 == 1)
-                module->connect(wire, RTLIL::State::S1);
-            else
-                log_abort();
-        }
-        else {
-            log_debug("%d is an output\n", l1);
-            const unsigned variable = l1 >> 1;
-            const bool invert = l1 & 1;
-            RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix?
-            wire = module->wire(wire_name);
-            if (!wire)
-                wire = createWireIfNotExists(module, l1);
-            else {
-                if (wire->port_input || wire->port_output) {
-                    RTLIL::Wire *new_wire = module->addWire(NEW_ID);
-                    module->connect(new_wire, wire);
-                    wire = new_wire;
-                }
-            }
-        }
-        wire->port_output = true;
-        outputs.push_back(wire);
-    }
-    std::getline(f, line); // Ignore up to start of next line
-
-    // TODO: Parse bad state properties
-    for (unsigned i = 0; i < B; ++i, ++line_count)
-        std::getline(f, line); // Ignore up to start of next line
-
-    // TODO: Parse invariant constraints
-    for (unsigned i = 0; i < C; ++i, ++line_count)
-        std::getline(f, line); // Ignore up to start of next line
-
-    // TODO: Parse justice properties
-    for (unsigned i = 0; i < J; ++i, ++line_count)
-        std::getline(f, line); // Ignore up to start of next line
-
-    // TODO: Parse fairness constraints
-    for (unsigned i = 0; i < F; ++i, ++line_count)
-        std::getline(f, line); // Ignore up to start of next line
-
-    // Parse AND
-    l1 = (I+L+1) << 1;
-    for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) {
-        l2 = parse_next_delta_literal(f, l1);
-        l3 = parse_next_delta_literal(f, l2);
-
-        log_debug("%d %d %d is an AND\n", l1, l2, l3);
-        log_assert(!(l1 & 1));
-        RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
-        RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
-        RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
-        module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
-    }
+	unsigned l1, l2, l3;
+	std::string line;
+
+	// Parse inputs
+	for (unsigned i = 1; i <= I; ++i) {
+		log_debug("%d is an input\n", i);
+		RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
+		wire->port_input = true;
+		log_assert(!wire->port_output);
+		inputs.push_back(wire);
+	}
+
+	// Parse latches
+	RTLIL::Wire *clk_wire = nullptr;
+	if (L > 0) {
+		log_assert(clk_name != "");
+		clk_wire = module->wire(clk_name);
+		log_assert(!clk_wire);
+		log_debug("Creating %s\n", clk_name.c_str());
+		clk_wire = module->addWire(clk_name);
+		clk_wire->port_input = true;
+		clk_wire->port_output = false;
+	}
+	l1 = (I+1) * 2;
+	for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
+		if (!(f >> l2))
+			log_error("Line %u cannot be interpreted as a latch!\n", line_count);
+		log_debug("%d %d is a latch\n", l1, l2);
+		RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
+		RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
+
+		module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
+
+		// Reset logic is optional in AIGER 1.9
+		if (f.peek() == ' ') {
+			if (!(f >> l3))
+				log_error("Line %u cannot be interpreted as a latch!\n", line_count);
+
+			if (l3 == 0)
+				q_wire->attributes["\\init"] = RTLIL::S0;
+			else if (l3 == 1)
+				q_wire->attributes["\\init"] = RTLIL::S1;
+			else if (l3 == l1) {
+				//q_wire->attributes["\\init"] = RTLIL::Sx;
+			}
+			else
+				log_error("Line %u has invalid reset literal for latch!\n", line_count);
+		}
+		else {
+			// AIGER latches are assumed to be initialized to zero
+			q_wire->attributes["\\init"] = RTLIL::S0;
+		}
+		latches.push_back(q_wire);
+	}
+
+	// Parse outputs
+	for (unsigned i = 0; i < O; ++i, ++line_count) {
+		if (!(f >> l1))
+			log_error("Line %u cannot be interpreted as an output!\n", line_count);
+
+		RTLIL::Wire *wire;
+		if (l1 == 0 || l1 == 1) {
+			wire = module->addWire(NEW_ID);
+			if (l1 == 0)
+				module->connect(wire, RTLIL::State::S0);
+			else if (l1 == 1)
+				module->connect(wire, RTLIL::State::S1);
+			else
+				log_abort();
+		}
+		else {
+			log_debug("%d is an output\n", l1);
+			const unsigned variable = l1 >> 1;
+			const bool invert = l1 & 1;
+			RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix?
+			wire = module->wire(wire_name);
+			if (!wire)
+				wire = createWireIfNotExists(module, l1);
+			else {
+				if (wire->port_input || wire->port_output) {
+					RTLIL::Wire *new_wire = module->addWire(NEW_ID);
+					module->connect(new_wire, wire);
+					wire = new_wire;
+				}
+			}
+		}
+		wire->port_output = true;
+		outputs.push_back(wire);
+	}
+	std::getline(f, line); // Ignore up to start of next line
+
+	// Parse bad properties
+	for (unsigned i = 0; i < B; ++i, ++line_count) {
+		if (!(f >> l1))
+			log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
+
+		log_debug("%d is a bad state property\n", l1);
+		RTLIL::Wire *wire = createWireIfNotExists(module, l1);
+		wire->port_output = true;
+		bad_properties.push_back(wire);
+	}
+	if (B > 0)
+		std::getline(f, line); // Ignore up to start of next line
+
+	// TODO: Parse invariant constraints
+	for (unsigned i = 0; i < C; ++i, ++line_count)
+		std::getline(f, line); // Ignore up to start of next line
+
+	// TODO: Parse justice properties
+	for (unsigned i = 0; i < J; ++i, ++line_count)
+		std::getline(f, line); // Ignore up to start of next line
+
+	// TODO: Parse fairness constraints
+	for (unsigned i = 0; i < F; ++i, ++line_count)
+		std::getline(f, line); // Ignore up to start of next line
+
+	// Parse AND
+	l1 = (I+L+1) << 1;
+	for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) {
+		l2 = parse_next_delta_literal(f, l1);
+		l3 = parse_next_delta_literal(f, l2);
+
+		log_debug("%d %d %d is an AND\n", l1, l2, l3);
+		log_assert(!(l1 & 1));
+		RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
+		RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
+		RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
+		module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
+	}
 }
 
 void AigerReader::post_process()
 {
-    pool<RTLIL::Module*> abc_carry_modules;
-    unsigned ci_count = 0, co_count = 0, flop_count = 0;
-    for (auto cell : boxes) {
-        RTLIL::Module* box_module = design->module(cell->type);
-        log_assert(box_module);
-
-        if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
-            RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
-            RTLIL::Wire* last_in = nullptr, *last_out = nullptr;
-            for (const auto &port_name : box_module->ports) {
-                RTLIL::Wire* w = box_module->wire(port_name);
-                log_assert(w);
-                if (w->port_input) {
-                    if (w->attributes.count("\\abc_carry_in")) {
-                        log_assert(!carry_in);
-                        carry_in = w;
-                    }
-                    log_assert(!last_in || last_in->port_id < w->port_id);
-                    last_in = w;
-                }
-                if (w->port_output) {
-                    if (w->attributes.count("\\abc_carry_out")) {
-                        log_assert(!carry_out);
-                        carry_out = w;
-                    }
-                    log_assert(!last_out || last_out->port_id < w->port_id);
-                    last_out = w;
-                }
-            }
-
-            if (carry_in != last_in) {
-                std::swap(box_module->ports[carry_in->port_id], box_module->ports[last_in->port_id]);
-                std::swap(carry_in->port_id, last_in->port_id);
-            }
-            if (carry_out != last_out) {
-                log_assert(last_out);
-                std::swap(box_module->ports[carry_out->port_id], box_module->ports[last_out->port_id]);
-                std::swap(carry_out->port_id, last_out->port_id);
-            }
-        }
-
-        bool flop = box_module->attributes.count("\\abc_flop");
-        log_assert(!flop || flop_count < flopNum);
-
-        // NB: Assume box_module->ports are sorted alphabetically
-        //     (as RTLIL::Module::fixup_ports() would do)
-        for (auto port_name : box_module->ports) {
-            RTLIL::Wire* w = box_module->wire(port_name);
-            log_assert(w);
-            RTLIL::SigSpec rhs;
-            RTLIL::Wire* wire = nullptr;
-            for (int i = 0; i < GetSize(w); i++) {
-                if (w->port_input) {
-                    log_assert(co_count < outputs.size());
-                    wire = outputs[co_count++];
-                    log_assert(wire);
-                    log_assert(wire->port_output);
-                    wire->port_output = false;
-
-                    if (flop && w->attributes.count("\\abc_flop_d")) {
-                        RTLIL::Wire* d = outputs[outputs.size() - flopNum + flop_count];
-                        log_assert(d);
-                        log_assert(d->port_output);
-                        d->port_output = false;
-                    }
-                }
-                if (w->port_output) {
-                    log_assert((piNum + ci_count) < inputs.size());
-                    wire = inputs[piNum + ci_count++];
-                    log_assert(wire);
-                    log_assert(wire->port_input);
-                    wire->port_input = false;
-
-                    if (flop && w->attributes.count("\\abc_flop_q")) {
-                        wire = inputs[piNum - flopNum + flop_count];
-                        log_assert(wire);
-                        log_assert(wire->port_input);
-                        wire->port_input = false;
-                    }
-                }
-                rhs.append(wire);
-            }
-            cell->setPort(port_name, rhs);
-        }
-
-        if (flop) flop_count++;
-    }
-
-    dict<RTLIL::IdString, int> wideports_cache;
-
-    if (!map_filename.empty()) {
-        std::ifstream mf(map_filename);
-        std::string type, symbol;
-        int variable, index;
-        while (mf >> type >> variable >> index >> symbol) {
-            RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
-            if (type == "input") {
-                log_assert(static_cast<unsigned>(variable) < inputs.size());
-                RTLIL::Wire* wire = inputs[variable];
-                log_assert(wire);
-                log_assert(wire->port_input);
-
-                if (index == 0) {
-                    // Cope with the fact that a CI might be identical
-                    // to a PI (necessary due to ABC); in those cases
-                    // simply connect the latter to the former
-                    RTLIL::Wire* existing = module->wire(escaped_s);
-                    if (!existing)
-                        module->rename(wire, escaped_s);
-                    else {
-                        wire->port_input = false;
-                        module->connect(wire, existing);
-                    }
-                }
-                else if (index > 0) {
-                    std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
-                    RTLIL::Wire* existing = module->wire(indexed_name);
-                    if (!existing) {
-                        module->rename(wire, indexed_name);
-                        if (wideports)
-                            wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
-                    }
-                    else {
-                        module->connect(wire, existing);
-                        wire->port_input = false;
-                    }
-                }
-            }
-            else if (type == "output") {
-                log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
-                RTLIL::Wire* wire = outputs[variable + co_count];
-                log_assert(wire);
-                log_assert(wire->port_output);
-                if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) {
-                    wire->port_output = false;
-                    continue;
-                }
-
-                if (index == 0) {
-                    // Cope with the fact that a CO might be identical
-                    // to a PO (necessary due to ABC); in those cases
-                    // simply connect the latter to the former
-                    RTLIL::Wire* existing = module->wire(escaped_s);
-                    if (!existing) {
-                        if (escaped_s.ends_with("$inout.out")) {
-                            wire->port_output = false;
-                            RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
-                            log_assert(in_wire);
-                            log_assert(in_wire->port_input && !in_wire->port_output);
-                            in_wire->port_output = true;
-                            module->connect(in_wire, wire);
-                        }
-                        else
-                            module->rename(wire, escaped_s);
-                    }
-                    else {
-                        wire->port_output = false;
-                        module->connect(wire, existing);
-                    }
-                }
-                else if (index > 0) {
-                    std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
-                    RTLIL::Wire* existing = module->wire(indexed_name);
-                    if (!existing) {
-                        if (escaped_s.ends_with("$inout.out")) {
-                            wire->port_output = false;
-                            RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
-                            log_assert(in_wire);
-                            log_assert(in_wire->port_input && !in_wire->port_output);
-                            in_wire->port_output = true;
-                            module->connect(in_wire, wire);
-                        }
-                        else {
-                            module->rename(wire, indexed_name);
-                            if (wideports)
-                                wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
-                        }
-                    }
-                    else {
-                        module->connect(wire, existing);
-                        wire->port_output = false;
-                    }
-                }
-            }
-            else if (type == "box") {
-                RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
-                if (cell) { // ABC could have optimised this box away
-                    module->rename(cell, escaped_s);
-                    RTLIL::Module* box_module = design->module(cell->type);
-                    log_assert(box_module);
-
-                    for (const auto &i : cell->connections()) {
-                        RTLIL::IdString port_name = i.first;
-                        RTLIL::SigSpec rhs = i.second;
-                        int index = 0;
-                        for (auto bit : rhs.bits()) {
-                            RTLIL::Wire* wire = bit.wire;
-                            RTLIL::IdString escaped_s = RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name)));
-                            if (index == 0)
-                                module->rename(wire, escaped_s);
-                            else if (index > 0) {
-                                module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index));
-                                if (wideports)
-                                    wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
-                            }
-                            index++;
-                        }
-                    }
-                }
-            }
-            else
-                log_error("Symbol type '%s' not recognised.\n", type.c_str());
-        }
-    }
-
-    for (auto &wp : wideports_cache) {
-        auto name = wp.first;
-        int width = wp.second + 1;
-
-        RTLIL::Wire *wire = module->wire(name);
-        if (wire)
-            module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
-
-        // Do not make ports with a mix of input/output into
-        // wide ports
-        bool port_input = false, port_output = false;
-        for (int i = 0; i < width; i++) {
-            RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
-            RTLIL::Wire *other_wire = module->wire(other_name);
-            if (other_wire) {
-                port_input = port_input || other_wire->port_input;
-                port_output = port_output || other_wire->port_output;
-            }
-        }
-        if ((port_input && port_output) || (!port_input && !port_output))
-            continue;
-
-        wire = module->addWire(name, width);
-        wire->port_input = port_input;
-        wire->port_output = port_output;
-
-        for (int i = 0; i < width; i++) {
-            RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
-            RTLIL::Wire *other_wire = module->wire(other_name);
-            if (other_wire) {
-                other_wire->port_input = false;
-                other_wire->port_output = false;
-                if (wire->port_input)
-                    module->connect(other_wire, SigSpec(wire, i));
-                else
-                    module->connect(SigSpec(wire, i), other_wire);
-            }
-        }
-    }
-
-    module->fixup_ports();
-    design->add(module);
-
-    design->selection_stack.emplace_back(false);
-    RTLIL::Selection& sel = design->selection_stack.back();
-    sel.select(module);
-
-    Pass::call(design, "clean");
-
-    design->selection_stack.pop_back();
-
-    for (auto cell : module->cells().to_vector()) {
-        if (cell->type != "$lut") continue;
-        auto y_port = cell->getPort("\\Y").as_bit();
-        if (y_port.wire->width == 1)
-            module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str()));
-        else
-            module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset));
-    }
+	pool<RTLIL::Module*> abc_carry_modules;
+	unsigned ci_count = 0, co_count = 0, flop_count = 0;
+	for (auto cell : boxes) {
+		RTLIL::Module* box_module = design->module(cell->type);
+		log_assert(box_module);
+
+		if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
+			RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
+			RTLIL::Wire* last_in = nullptr, *last_out = nullptr;
+			for (const auto &port_name : box_module->ports) {
+				RTLIL::Wire* w = box_module->wire(port_name);
+				log_assert(w);
+				if (w->port_input) {
+					if (w->attributes.count("\\abc_carry_in")) {
+						log_assert(!carry_in);
+						carry_in = w;
+					}
+					log_assert(!last_in || last_in->port_id < w->port_id);
+					last_in = w;
+				}
+				if (w->port_output) {
+					if (w->attributes.count("\\abc_carry_out")) {
+						log_assert(!carry_out);
+						carry_out = w;
+					}
+					log_assert(!last_out || last_out->port_id < w->port_id);
+					last_out = w;
+				}
+			}
+
+			if (carry_in != last_in) {
+				std::swap(box_module->ports[carry_in->port_id], box_module->ports[last_in->port_id]);
+				std::swap(carry_in->port_id, last_in->port_id);
+			}
+			if (carry_out != last_out) {
+				log_assert(last_out);
+				std::swap(box_module->ports[carry_out->port_id], box_module->ports[last_out->port_id]);
+				std::swap(carry_out->port_id, last_out->port_id);
+			}
+		}
+
+		bool flop = box_module->attributes.count("\\abc_flop");
+		log_assert(!flop || flop_count < flopNum);
+
+		// NB: Assume box_module->ports are sorted alphabetically
+		//     (as RTLIL::Module::fixup_ports() would do)
+		for (auto port_name : box_module->ports) {
+			RTLIL::Wire* w = box_module->wire(port_name);
+			log_assert(w);
+			RTLIL::SigSpec rhs;
+			RTLIL::Wire* wire = nullptr;
+			for (int i = 0; i < GetSize(w); i++) {
+				if (w->port_input) {
+					log_assert(co_count < outputs.size());
+					wire = outputs[co_count++];
+					log_assert(wire);
+					log_assert(wire->port_output);
+					wire->port_output = false;
+
+					if (flop && w->attributes.count("\\abc_flop_d")) {
+						RTLIL::Wire* d = outputs[outputs.size() - flopNum + flop_count];
+						log_assert(d);
+						log_assert(d->port_output);
+						d->port_output = false;
+					}
+				}
+				if (w->port_output) {
+					log_assert((piNum + ci_count) < inputs.size());
+					wire = inputs[piNum + ci_count++];
+					log_assert(wire);
+					log_assert(wire->port_input);
+					wire->port_input = false;
+
+					if (flop && w->attributes.count("\\abc_flop_q")) {
+						wire = inputs[piNum - flopNum + flop_count];
+						log_assert(wire);
+						log_assert(wire->port_input);
+						wire->port_input = false;
+					}
+				}
+				rhs.append(wire);
+			}
+			cell->setPort(port_name, rhs);
+		}
+
+		if (flop) flop_count++;
+	}
+
+	dict<RTLIL::IdString, int> wideports_cache;
+
+	if (!map_filename.empty()) {
+		std::ifstream mf(map_filename);
+		std::string type, symbol;
+		int variable, index;
+		while (mf >> type >> variable >> index >> symbol) {
+			RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
+			if (type == "input") {
+				log_assert(static_cast<unsigned>(variable) < inputs.size());
+				RTLIL::Wire* wire = inputs[variable];
+				log_assert(wire);
+				log_assert(wire->port_input);
+
+				if (index == 0) {
+					// Cope with the fact that a CI might be identical
+					// to a PI (necessary due to ABC); in those cases
+					// simply connect the latter to the former
+					RTLIL::Wire* existing = module->wire(escaped_s);
+					if (!existing)
+						module->rename(wire, escaped_s);
+					else {
+						wire->port_input = false;
+						module->connect(wire, existing);
+					}
+				}
+				else if (index > 0) {
+					std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
+					RTLIL::Wire* existing = module->wire(indexed_name);
+					if (!existing) {
+						module->rename(wire, indexed_name);
+						if (wideports)
+							wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
+					}
+					else {
+						module->connect(wire, existing);
+						wire->port_input = false;
+					}
+				}
+			}
+			else if (type == "output") {
+				log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
+				RTLIL::Wire* wire = outputs[variable + co_count];
+				log_assert(wire);
+				log_assert(wire->port_output);
+				if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) {
+					wire->port_output = false;
+					continue;
+				}
+
+				if (index == 0) {
+					// Cope with the fact that a CO might be identical
+					// to a PO (necessary due to ABC); in those cases
+					// simply connect the latter to the former
+					RTLIL::Wire* existing = module->wire(escaped_s);
+					if (!existing) {
+						if (escaped_s.ends_with("$inout.out")) {
+							wire->port_output = false;
+							RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
+							log_assert(in_wire);
+							log_assert(in_wire->port_input && !in_wire->port_output);
+							in_wire->port_output = true;
+							module->connect(in_wire, wire);
+						}
+						else
+							module->rename(wire, escaped_s);
+					}
+					else {
+						wire->port_output = false;
+						module->connect(wire, existing);
+					}
+				}
+				else if (index > 0) {
+					std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
+					RTLIL::Wire* existing = module->wire(indexed_name);
+					if (!existing) {
+						if (escaped_s.ends_with("$inout.out")) {
+							wire->port_output = false;
+							RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
+							log_assert(in_wire);
+							log_assert(in_wire->port_input && !in_wire->port_output);
+							in_wire->port_output = true;
+							module->connect(in_wire, wire);
+						}
+						else {
+							module->rename(wire, indexed_name);
+							if (wideports)
+								wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
+						}
+					}
+					else {
+						module->connect(wire, existing);
+						wire->port_output = false;
+					}
+				}
+			}
+			else if (type == "box") {
+				RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
+				if (cell) { // ABC could have optimised this box away
+					module->rename(cell, escaped_s);
+					RTLIL::Module* box_module = design->module(cell->type);
+					log_assert(box_module);
+
+					for (const auto &i : cell->connections()) {
+						RTLIL::IdString port_name = i.first;
+						RTLIL::SigSpec rhs = i.second;
+						int index = 0;
+						for (auto bit : rhs.bits()) {
+							RTLIL::Wire* wire = bit.wire;
+							RTLIL::IdString escaped_s = RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name)));
+							if (index == 0)
+								module->rename(wire, escaped_s);
+							else if (index > 0) {
+								module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index));
+								if (wideports)
+									wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
+							}
+							index++;
+						}
+					}
+				}
+			}
+			else
+				log_error("Symbol type '%s' not recognised.\n", type.c_str());
+		}
+	}
+
+	for (auto &wp : wideports_cache) {
+		auto name = wp.first;
+		int width = wp.second + 1;
+
+		RTLIL::Wire *wire = module->wire(name);
+		if (wire)
+			module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
+
+		// Do not make ports with a mix of input/output into
+		// wide ports
+		bool port_input = false, port_output = false;
+		for (int i = 0; i < width; i++) {
+			RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
+			RTLIL::Wire *other_wire = module->wire(other_name);
+			if (other_wire) {
+				port_input = port_input || other_wire->port_input;
+				port_output = port_output || other_wire->port_output;
+			}
+		}
+		if ((port_input && port_output) || (!port_input && !port_output))
+			continue;
+
+		wire = module->addWire(name, width);
+		wire->port_input = port_input;
+		wire->port_output = port_output;
+
+		for (int i = 0; i < width; i++) {
+			RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
+			RTLIL::Wire *other_wire = module->wire(other_name);
+			if (other_wire) {
+				other_wire->port_input = false;
+				other_wire->port_output = false;
+				if (wire->port_input)
+					module->connect(other_wire, SigSpec(wire, i));
+				else
+					module->connect(SigSpec(wire, i), other_wire);
+			}
+		}
+	}
+
+	module->fixup_ports();
+	design->add(module);
+
+	design->selection_stack.emplace_back(false);
+	RTLIL::Selection& sel = design->selection_stack.back();
+	sel.select(module);
+
+	Pass::call(design, "clean");
+
+	design->selection_stack.pop_back();
+
+	for (auto cell : module->cells().to_vector()) {
+		if (cell->type != "$lut") continue;
+		auto y_port = cell->getPort("\\Y").as_bit();
+		if (y_port.wire->width == 1)
+			module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str()));
+		else
+			module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset));
+	}
 }
 
 struct AigerFrontend : public Frontend {
-    AigerFrontend() : Frontend("aiger", "read AIGER file") { }
-    void help() YS_OVERRIDE
-    {
-        //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-        log("\n");
-        log("    read_aiger [options] [filename]\n");
-        log("\n");
-        log("Load module from an AIGER file into the current design.\n");
-        log("\n");
-        log("    -module_name <module_name>\n");
-        log("        Name of module to be created (default: <filename>)\n");
-        log("\n");
-        log("    -clk_name <wire_name>\n");
-        log("        AIGER latches to be transformed into posedge DFFs clocked by wire of");
-        log("        this name (default: clk)\n");
-        log("\n");
-        log("    -map <filename>\n");
-        log("        read file with port and latch symbols\n");
-        log("\n");
-        log("    -wideports\n");
-        log("        Merge ports that match the pattern 'name[int]' into a single\n");
-        log("        multi-bit port 'name'.\n");
-        log("\n");
-    }
-    void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-    {
-        log_header(design, "Executing AIGER frontend.\n");
-
-        RTLIL::IdString clk_name = "\\clk";
-        RTLIL::IdString module_name;
-        std::string map_filename;
-        bool wideports = false;
-
-        size_t argidx;
-        for (argidx = 1; argidx < args.size(); argidx++) {
-                std::string arg = args[argidx];
-                if (arg == "-module_name" && argidx+1 < args.size()) {
-                        module_name = RTLIL::escape_id(args[++argidx]);
-                        continue;
-                }
-                if (arg == "-clk_name" && argidx+1 < args.size()) {
-                        clk_name = RTLIL::escape_id(args[++argidx]);
-                        continue;
-                }
-                if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
-                        map_filename = args[++argidx];
-                        continue;
-                }
-                if (arg == "-wideports") {
-                        wideports = true;
-                        continue;
-                }
-                break;
-        }
-        extra_args(f, filename, args, argidx);
-
-        if (module_name.empty()) {
+	AigerFrontend() : Frontend("aiger", "read AIGER file") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    read_aiger [options] [filename]\n");
+		log("\n");
+		log("Load module from an AIGER file into the current design.\n");
+		log("\n");
+		log("    -module_name <module_name>\n");
+		log("        Name of module to be created (default: <filename>)\n");
+		log("\n");
+		log("    -clk_name <wire_name>\n");
+		log("        AIGER latches to be transformed into posedge DFFs clocked by wire of");
+		log("        this name (default: clk)\n");
+		log("\n");
+		log("    -map <filename>\n");
+		log("        read file with port and latch symbols\n");
+		log("\n");
+		log("    -wideports\n");
+		log("        Merge ports that match the pattern 'name[int]' into a single\n");
+		log("        multi-bit port 'name'.\n");
+		log("\n");
+	}
+	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing AIGER frontend.\n");
+
+		RTLIL::IdString clk_name = "\\clk";
+		RTLIL::IdString module_name;
+		std::string map_filename;
+		bool wideports = false;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			std::string arg = args[argidx];
+			if (arg == "-module_name" && argidx+1 < args.size()) {
+				module_name = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (arg == "-clk_name" && argidx+1 < args.size()) {
+				clk_name = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
+				map_filename = args[++argidx];
+				continue;
+			}
+			if (arg == "-wideports") {
+				wideports = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(f, filename, args, argidx);
+
+		if (module_name.empty()) {
 #ifdef _WIN32
-            char fname[_MAX_FNAME];
-            _splitpath(filename.c_str(), NULL /* drive */, NULL /* dir */, fname, NULL /* ext */)
-            module_name = fname;
+			char fname[_MAX_FNAME];
+			_splitpath(filename.c_str(), NULL /* drive */, NULL /* dir */, fname, NULL /* ext */)
+				module_name = fname;
 #else
-            char* bn = strdup(filename.c_str());
-            module_name = RTLIL::escape_id(bn);
-            free(bn);
+			char* bn = strdup(filename.c_str());
+			module_name = RTLIL::escape_id(bn);
+			free(bn);
 #endif
-        }
+		}
 
-        AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
-        reader.parse_aiger();
-    }
+		AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
+		reader.parse_aiger();
+	}
 } AigerFrontend;
 
 YOSYS_NAMESPACE_END
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 28f40279b..7d6d70b2c 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -42,6 +42,7 @@ struct AigerReader
     std::vector<RTLIL::Wire*> inputs;
     std::vector<RTLIL::Wire*> latches;
     std::vector<RTLIL::Wire*> outputs;
+    std::vector<RTLIL::Wire*> bad_properties;
     std::vector<RTLIL::Cell*> boxes;
 
     AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 83993eea9..b5b968e9e 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -154,6 +154,7 @@ std::string AST::type2str(AstNodeType type)
 	X(AST_GENIF)
 	X(AST_GENCASE)
 	X(AST_GENBLOCK)
+	X(AST_TECALL)
 	X(AST_POSEDGE)
 	X(AST_NEGEDGE)
 	X(AST_EDGE)
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 46d482f1a..b8cde060e 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -137,7 +137,8 @@ namespace AST
 		AST_GENIF,
 		AST_GENCASE,
 		AST_GENBLOCK,
-
+		AST_TECALL,
+		
 		AST_POSEDGE,
 		AST_NEGEDGE,
 		AST_EDGE,
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d2651c9aa..32ed401eb 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1575,6 +1575,37 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			delete always;
 		} break;
 
+	case AST_TECALL: {
+			int sz = children.size();
+			if (str == "$info") {
+				if (sz > 0)
+					log_file_info(filename, linenum, "%s.\n", children[0]->str.c_str());
+				else
+					log_file_info(filename, linenum, "\n");
+			} else if (str == "$warning") {
+				if (sz > 0)
+					log_file_warning(filename, linenum, "%s.\n", children[0]->str.c_str());
+				else
+					log_file_warning(filename, linenum, "\n");
+			} else if (str == "$error") {
+				if (sz > 0)
+					log_file_error(filename, linenum, "%s.\n", children[0]->str.c_str());
+				else
+					log_file_error(filename, linenum, "\n");
+			} else if (str == "$fatal") {
+				// TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish()
+				// if no parameter is given, default value is 1
+				// dollar_finish(sz ? children[0] : 1);
+				// perhaps create & use log_file_fatal()
+				if (sz > 0)
+					log_file_error(filename, linenum, "FATAL: %s.\n", children[0]->str.c_str());
+				else
+					log_file_error(filename, linenum, "FATAL.\n");
+			} else {
+				log_file_error(filename, linenum, "Unknown elabortoon system task '%s'.\n", str.c_str());
+			}
+		} break;
+
 	case AST_FCALL: {
 			if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq")
 			{
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 9558bbfb9..3c612472d 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -311,6 +311,11 @@ supply1 { return TOK_SUPPLY1; }
 	return TOK_ID;
 }
 
+"$"(info|warning|error|fatal) {
+	frontend_verilog_yylval.string = new std::string(yytext);
+	return TOK_ELAB_TASK;
+}
+
 "$signed"   { return TOK_TO_SIGNED; }
 "$unsigned" { return TOK_TO_UNSIGNED; }
 
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ccdab987f..a034f9601 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -133,7 +133,7 @@ struct specify_rise_fall {
 }
 
 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
-%token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER
+%token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_ELAB_TASK
 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
@@ -1557,6 +1557,15 @@ cell_port:
 		astbuf2->children.push_back(node);
 		delete $3;
 		free_attr($1);
+	} |
+	attr '.' TOK_ID {
+		AstNode *node = new AstNode(AST_ARGUMENT);
+		node->str = *$3;
+		astbuf2->children.push_back(node);
+		node->children.push_back(new AstNode(AST_IDENTIFIER));
+		node->children.back()->str = *$3;
+		delete $3;
+		free_attr($1);
 	};
 
 always_stmt:
@@ -2167,6 +2176,15 @@ gen_stmt:
 		if ($6 != NULL)
 			delete $6;
 		ast_stack.pop_back();
+	} |
+	TOK_ELAB_TASK {
+		AstNode *node = new AstNode(AST_TECALL);
+		node->str = *$1;
+		delete $1;
+		ast_stack.back()->children.push_back(node);
+		ast_stack.push_back(node);
+	} opt_arg_list ';'{
+		ast_stack.pop_back();		
 	};
 
 gen_stmt_block:
diff --git a/kernel/log.cc b/kernel/log.cc
index fa74a6a3c..a7820950c 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -277,11 +277,22 @@ void log_file_warning(const std::string &filename, int lineno,
 	va_list ap;
 	va_start(ap, format);
 	std::string prefix = stringf("%s:%d: Warning: ",
-				     filename.c_str(), lineno);
+			filename.c_str(), lineno);
 	logv_warning_with_prefix(prefix.c_str(), format, ap);
 	va_end(ap);
 }
 
+void log_file_info(const std::string &filename, int lineno,
+                      const char *format, ...)
+{
+	va_list ap;
+	va_start(ap, format);
+	std::string fmt = stringf("%s:%d: Info: %s",
+			filename.c_str(), lineno, format);
+	logv(fmt.c_str(), ap);
+	va_end(ap);
+}
+
 YS_ATTRIBUTE(noreturn)
 static void logv_error_with_prefix(const char *prefix,
                                    const char *format, va_list ap)
diff --git a/kernel/log.h b/kernel/log.h
index e6afae716..3e1facae8 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -80,6 +80,7 @@ void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
 
 // Log with filename to report a problem in a source file.
 void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
+void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
 
 void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
 YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);
diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py
index 9f2c72915..9e5727499 100644
--- a/misc/py_wrap_generator.py
+++ b/misc/py_wrap_generator.py
@@ -2026,7 +2026,6 @@ def gen_wrappers(filename, debug_level_ = 0):
 #include <boost/python/wrapper.hpp>
 #include <boost/python/call.hpp>
 #include <boost/python.hpp>
-#include <boost/log/exceptions.hpp>
 
 USING_YOSYS_NAMESPACE
 
diff --git a/tests/aiger/and.aig b/tests/aiger/and.aig
deleted file mode 100644
index da0fa0719..000000000
--- a/tests/aiger/and.aig
+++ /dev/null
@@ -1,3 +0,0 @@
-aig 3 2 0 1 1
-6
-
\ No newline at end of file
diff --git a/tests/aiger/and.aag b/tests/aiger/and_.aag
index d1ef2c5a5..cadd505f0 100644
--- a/tests/aiger/and.aag
+++ b/tests/aiger/and_.aag
@@ -3,3 +3,6 @@ aag 3 2 0 1 1
 4
 6
 6 2 4
+i0 pi0
+i1 pi1
+o0 po0
diff --git a/tests/aiger/and_.aig b/tests/aiger/and_.aig
new file mode 100644
index 000000000..13c7a0c17
--- /dev/null
+++ b/tests/aiger/and_.aig
@@ -0,0 +1,5 @@
+aig 3 2 0 1 1
+6
+i0 pi0
+i1 pi1
+o0 po0
diff --git a/tests/aiger/buffer.aag b/tests/aiger/buffer.aag
index 94a6fb1ed..211106ed6 100644
--- a/tests/aiger/buffer.aag
+++ b/tests/aiger/buffer.aag
@@ -1,3 +1,5 @@
 aag 1 1 0 1 0
 2
 2
+i0 pi0
+o0 po0
diff --git a/tests/aiger/buffer.aig b/tests/aiger/buffer.aig
index 0c715fdeb..01df6f1cf 100644
--- a/tests/aiger/buffer.aig
+++ b/tests/aiger/buffer.aig
@@ -1,2 +1,4 @@
 aig 1 1 0 1 0
 2
+i0 pi0
+o0 po0
diff --git a/tests/aiger/cnt1.aag b/tests/aiger/cnt1.aag
index ce4f28fcb..75598862c 100644
--- a/tests/aiger/cnt1.aag
+++ b/tests/aiger/cnt1.aag
@@ -1,3 +1,4 @@
 aag 1 0 1 0 0 1
 2 3
 2
+b0 po0
diff --git a/tests/aiger/cnt1.aig b/tests/aiger/cnt1.aig
index 8d0ba13b1..6fcf62522 100644
--- a/tests/aiger/cnt1.aig
+++ b/tests/aiger/cnt1.aig
@@ -1,3 +1,4 @@
 aig 1 0 1 0 0 1
 3
 2
+b0 po0
diff --git a/tests/aiger/cnt1e.aag b/tests/aiger/cnt1e.aag
index 6db3f0ffd..35cd5a482 100644
--- a/tests/aiger/cnt1e.aag
+++ b/tests/aiger/cnt1e.aag
@@ -6,3 +6,4 @@ aag 5 1 1 0 3 1
 8 4 2
 10 9 7
 b0 AIGER_NEVER
+i0 po0
diff --git a/tests/aiger/cnt1e.aig b/tests/aiger/cnt1e.aig
index d8d159f11..7284dd42a 100644
--- a/tests/aiger/cnt1e.aig
+++ b/tests/aiger/cnt1e.aig
@@ -1,4 +1,5 @@
 aig 5 1 1 0 3 1
 10
 4
-

b0 AIGER_NEVER
+

i0 po0
+b0 AIGER_NEVER
diff --git a/tests/aiger/false.aag b/tests/aiger/false.aag
index 421e64a91..bab4a06a6 100644
--- a/tests/aiger/false.aag
+++ b/tests/aiger/false.aag
@@ -1,2 +1,3 @@
 aag 0 0 0 1 0
 0
+o0 po0
diff --git a/tests/aiger/false.aig b/tests/aiger/false.aig
index ad7d039fa..4dc442d7b 100644
--- a/tests/aiger/false.aig
+++ b/tests/aiger/false.aig
@@ -1,2 +1,3 @@
 aig 0 0 0 1 0
 0
+o0 po0
diff --git a/tests/aiger/inverter.aag b/tests/aiger/inverter.aag
index ff7c28542..428bad9e4 100644
--- a/tests/aiger/inverter.aag
+++ b/tests/aiger/inverter.aag
@@ -1,3 +1,5 @@
 aag 1 1 0 1 0
 2
 3
+i0 pi0
+o0 po0
diff --git a/tests/aiger/inverter.aig b/tests/aiger/inverter.aig
index 525d82392..5bec90ae3 100644
--- a/tests/aiger/inverter.aig
+++ b/tests/aiger/inverter.aig
@@ -1,2 +1,4 @@
 aig 1 1 0 1 0
 3
+i0 pi0
+o0 po0
diff --git a/tests/aiger/notcnt1e.aag b/tests/aiger/notcnt1e.aag
index 141c864f7..2ed645d84 100644
--- a/tests/aiger/notcnt1e.aag
+++ b/tests/aiger/notcnt1e.aag
@@ -6,3 +6,4 @@ aag 5 1 1 0 3 1
 8 4 2
 10 9 7
 b0 AIGER_NEVER
+i0 pi0
diff --git a/tests/aiger/notcnt1e.aig b/tests/aiger/notcnt1e.aig
index 7c85a7290..fd7e94508 100644
--- a/tests/aiger/notcnt1e.aig
+++ b/tests/aiger/notcnt1e.aig
@@ -1,4 +1,5 @@
 aig 5 1 1 0 3 1
 10
 5
-

b0 AIGER_NEVER
+

i0 pi0
+b0 AIGER_NEVER
diff --git a/tests/aiger/or.aig b/tests/aiger/or.aig
deleted file mode 100644
index 75c9e4480..000000000
--- a/tests/aiger/or.aig
+++ /dev/null
@@ -1,3 +0,0 @@
-aig 3 2 0 1 1
-7
-

\ No newline at end of file
diff --git a/tests/aiger/or.aag b/tests/aiger/or_.aag
index f780e339f..0f619dba3 100644
--- a/tests/aiger/or.aag
+++ b/tests/aiger/or_.aag
@@ -3,3 +3,6 @@ aag 3 2 0 1 1
 4
 7
 6 3 5
+i0 pi0
+i1 pi1
+o0 po0
diff --git a/tests/aiger/or_.aig b/tests/aiger/or_.aig
new file mode 100644
index 000000000..051687512
--- /dev/null
+++ b/tests/aiger/or_.aig
@@ -0,0 +1,5 @@
+aig 3 2 0 1 1
+7
+
i0 pi0
+i1 pi1
+o0 po0
diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index e0a34f023..e56d0fa80 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -1,24 +1,37 @@
 #!/bin/bash
 
-OPTIND=1
-seed=""    # default to no seed specified
-while getopts "S:" opt
-do
-    case "$opt" in
-	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
-	   seed="SEED=$arg" ;;
-    esac
-done
-shift "$((OPTIND-1))"
-
-# check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
-  echo "$0: Error: Icarus Verilog 'iverilog' not found."
-  exit 1
-fi
+set -e
 
-echo "===== AAG ======"
-${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
+for aag in *.aag; do
+    # Since ABC cannot read *.aag, read the *.aig instead
+    # (which would have been created by the reference aig2aig utility)
+    ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
+    ../../yosys -p "
+read_verilog ${aag%.*}_ref.v
+prep
+design -stash gold
+read_aiger -clk_name clock $aag
+prep
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 16 miter
+"
+done
 
-echo "===== AIG ======"
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aig EXTRA_FLAGS="-f aiger"
+for aig in *.aig; do
+    ../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v"
+    ../../yosys -p "
+read_verilog ${aig%.*}_ref.v
+prep
+design -stash gold
+read_aiger -clk_name clock $aig
+prep
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 16 miter
+"
+done
diff --git a/tests/aiger/toggle.aag b/tests/aiger/toggle.aag
index 09651012d..b1a1582d7 100644
--- a/tests/aiger/toggle.aag
+++ b/tests/aiger/toggle.aag
@@ -2,3 +2,5 @@ aag 1 0 1 2 0
 2 3
 2
 3
+o0 po0
+o1 po1
diff --git a/tests/aiger/toggle.aig b/tests/aiger/toggle.aig
index b69e21aaf..68b41763f 100644
--- a/tests/aiger/toggle.aig
+++ b/tests/aiger/toggle.aig
@@ -2,3 +2,5 @@ aig 1 0 1 2 0
 3
 2
 3
+o0 po0
+o1 po1
diff --git a/tests/aiger/true.aag b/tests/aiger/true.aag
index 366893648..66a9eab46 100644
--- a/tests/aiger/true.aag
+++ b/tests/aiger/true.aag
@@ -1,2 +1,3 @@
 aag 0 0 0 1 0
 1
+o0 po0
diff --git a/tests/aiger/true.aig b/tests/aiger/true.aig
index 10086f389..f9bad6000 100644
--- a/tests/aiger/true.aig
+++ b/tests/aiger/true.aig
@@ -1,2 +1,3 @@
 aig 0 0 0 1 0
 1
+o0 po0
diff --git a/tests/simple/implicit_ports.v b/tests/simple/implicit_ports.v
new file mode 100644
index 000000000..8b0a6f386
--- /dev/null
+++ b/tests/simple/implicit_ports.v
@@ -0,0 +1,16 @@
+// Test implicit port connections
+module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
+	assign cout = cin;
+	assign result = a + b;
+endmodule
+
+module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
+	wire cin = 1;
+	alu alu (
+		.a(a),
+		.b, // Implicit connection is equivalent to .b(b)
+		.cin(), // Explicitely unconnected
+		.cout(cout),
+		.result(alu_result)
+	);
+endmodule
diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh
index aaa1cf940..967ac49f2 100755
--- a/tests/simple/run-test.sh
+++ b/tests/simple/run-test.sh
@@ -17,4 +17,5 @@ if ! which iverilog > /dev/null ; then
   exit 1
 fi
 
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v
+shopt -s nullglob
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.{sv,v}
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 920474a84..23964a751 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -89,6 +89,13 @@ done
 
 compile_and_run() {
 	exe="$1"; output="$2"; shift 2
+	ext=${1##*.}
+	if [ "$ext" == "sv" ]; then
+		language_gen="-g2012"
+	else
+		language_gen="-g2005"
+	fi
+
 	if $use_modelsim; then
 		altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
 		/opt/altera/$altver/modelsim_ase/bin/vlib work
@@ -99,7 +106,7 @@ compile_and_run() {
 		/opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
 		/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
 	else
-		iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
+		iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
 		vvp -n "$exe"
 	fi
 }
@@ -110,7 +117,7 @@ for fn
 do
 	bn=${fn%.*}
 	ext=${fn##*.}
-	if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
+	if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
 		echo "Invalid argument: $fn" >&2
 		exit 1
 	fi
@@ -123,6 +130,10 @@ do
 		echo -n "Test: $bn "
 	fi
 
+	if [ "$ext" == sv ]; then
+		frontend="$frontend -sv"
+	fi
+
 	rm -f ${bn}.{err,log,skip}
 	mkdir -p ${bn}.out
 	rm -rf ${bn}.out/*
@@ -135,9 +146,10 @@ do
 		rm -f ${bn}_ref.fir
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
+		elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
+			"$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v"
 		else
-			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
-			frontend="verilog -noblackbox"
+			cp ../${fn} ${bn}_ref.${ext}
 		fi
 
 		if [ ! -f ../${bn}_tb.v ]; then
diff --git a/tests/various/elab_sys_tasks.sv b/tests/various/elab_sys_tasks.sv
new file mode 100644
index 000000000..774d85b32
--- /dev/null
+++ b/tests/various/elab_sys_tasks.sv
@@ -0,0 +1,30 @@
+module test;
+localparam X=1;
+genvar i;
+generate
+if (X == 1)
+  $info("X is 1");
+if (X == 1)
+  $warning("X is 1");
+else
+  $error("X is not 1");
+case (X)
+  1: $info("X is 1 in a case statement");
+endcase
+//case (X-1)
+//  1: $warn("X is 2");
+//  default: $warn("X might be anything in a case statement");
+//endcase
+for (i = 0; i < 3; i = i + 1)
+begin
+  case(i)
+    0: $info;
+    1: $warning;
+    default: $info("default case statemnent");
+  endcase
+end
+
+$info("This is a standalone $info(). Next $info has no parameters");
+$info;
+endgenerate
+endmodule
diff --git a/tests/various/elab_sys_tasks.ys b/tests/various/elab_sys_tasks.ys
new file mode 100644
index 000000000..45bee3a60
--- /dev/null
+++ b/tests/various/elab_sys_tasks.ys
@@ -0,0 +1 @@
+read_verilog -sv elab_sys_tasks.sv