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* | | | Stub for binary AIGEREddie Hung2019-02-081-3/+8
* | | | RefactorEddie Hung2019-02-061-1/+8
* | | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaigEddie Hung2019-02-067-50/+172
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| * | | RefactorEddie Hung2019-02-061-21/+5
| * | | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
| * | | Add INIT parameter to all ff/latch cellsEddie Hung2019-02-062-43/+86
| * | | Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
| * | | Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
| * | | Extend testcaseEddie Hung2019-02-061-2/+34
| * | | Add testcaseEddie Hung2019-02-061-0/+10
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| * / Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::...Clifford Wolf2019-02-061-1/+1
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* | Revert most of autotest.sh; for non *.v use Yosys to translateEddie Hung2019-02-061-7/+9
* | Rename ASCII testsEddie Hung2019-02-0615-0/+0
* | WIPEddie Hung2019-02-063-0/+247
* | Add testsEddie Hung2019-02-0416-8/+109
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* Merge pull request #798 from mmicko/masterClifford Wolf2019-01-271-1/+1
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| * Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
* | Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
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| * | write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
* | | Merge branch 'whitequark-write_verilog_keyword'Clifford Wolf2019-01-275-69/+27
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| * | Remove asicworld tests for (unsupported) switch-level modellingClifford Wolf2019-01-274-69/+0
| * | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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* | Merge pull request #796 from whitequark/proc_clean_typoDavid Shah2019-01-251-1/+1
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| * proc_clean: fix critical typo.whitequark2019-01-231-1/+1
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* Merge pull request #793 from whitequark/proc_clean_fix_fully_defClifford Wolf2019-01-191-1/+7
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| * proc_clean: fix fully def check to consider compare/signal length.whitequark2019-01-181-1/+7
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* Cleanups in igloo2 example designClifford Wolf2019-01-176-7/+4
* Add SF2 IO buffer insertionClifford Wolf2019-01-176-3/+171
* Improve Igloo2 exampleClifford Wolf2019-01-178-22/+41
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
* Add optional nullstr argument to log_id()Clifford Wolf2019-01-151-1/+3
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
* Merge pull request #788 from whitequark/masterClifford Wolf2019-01-151-5/+17
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| * manual: document some gates.whitequark2019-01-141-9/+11
| * manual: explain $tribuf cell.whitequark2019-01-141-0/+10
* | Merge pull request #787 from whitequark/flowmap_relaxClifford Wolf2019-01-157-35/+776
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| * flowmap: clean up terminology.whitequark2019-01-081-17/+18
| * flowmap: implement depth relaxation.whitequark2019-01-087-22/+762
* | Improve igloo2 exampleClifford Wolf2019-01-084-5/+29
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* Fix typo in manualClifford Wolf2019-01-071-1/+1
* Bugfix in $memrd sharingClifford Wolf2019-01-071-2/+6
* Merge pull request #782 from whitequark/flowmap_dfsClifford Wolf2019-01-073-124/+243
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| * flowmap: construct a max-volume max-flow min-cut, not just any one.whitequark2019-01-061-7/+10
| * flowmap: add -minlut option, to allow postprocessing with opt_lut.whitequark2019-01-041-7/+21
| * flowmap: cleanup for clarity. NFCI.whitequark2019-01-043-107/+179
| * flowmap: improve debug graph output. NFC.whitequark2019-01-041-47/+76
| * flowmap: add link to longer version of paper. NFC.whitequark2019-01-041-2/+3
* | Switch "bugpoint" from system() to run_command()Clifford Wolf2019-01-071-1/+1
* | Merge pull request #783 from whitequark/bugpointClifford Wolf2019-01-072-1/+370
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