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* Add author nameEddie Hung2019-03-191-0/+1
* Add aiger tests to make testsEddie Hung2019-02-191-0/+1
* Merge branch 'master' into read_aigerEddie Hung2019-02-190-0/+0
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| * Merge pull request #805 from eddiehung/dff_initEddie Hung2019-02-194-2/+76
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* | | Fix for using POSIX basenameEddie Hung2019-02-191-2/+4
* | | Missing OSX headers?Eddie Hung2019-02-171-0/+5
* | | Revert "Missing headers for Xcode?"Eddie Hung2019-02-171-2/+0
* | | Merge branch 'dff_init' into read_aigerEddie Hung2019-02-173-104/+56
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| * | Instead of INIT param on cells, use initial statement with hier ref asEddie Hung2019-02-171-18/+13
| * | Revert "Add INIT parameter to all ff/latch cells"Eddie Hung2019-02-172-86/+43
* | | read_aiger to ignore line after ands for ascii, not binaryEddie Hung2019-02-171-2/+1
* | | One more merge conflictEddie Hung2019-02-171-6/+1
* | | Merge branch 'dff_init' into read_aigerEddie Hung2019-02-170-0/+0
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| * | Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-179-100/+345
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* | | Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-179-100/+349
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| * | Merge pull request #811 from ucb-bar/firrtlfixesClifford Wolf2019-02-176-56/+298
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| | * | Removed unused variables, functions.Jim Lawson2019-02-151-20/+0
| | * | Append (instead of over-writing) EXTRA_FLAGSJim Lawson2019-02-151-1/+1
| | * | Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-155-55/+317
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| * | Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| * | Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
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| | * | write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| * | | Merge pull request #806 from daveshah1/fsm_opt_no_resetClifford Wolf2019-02-121-1/+2
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| | * | | fsm_opt: Fix runtime error for FSMs without a reset stateDavid Shah2019-02-071-1/+2
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* | | | Missing headers for Xcode?Eddie Hung2019-02-121-0/+2
* | | | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aigerEddie Hung2019-02-121-3/+1
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| * | | | Do not break for constraintsEddie Hung2019-02-111-1/+0
| * | | | No increment line_count for binary ANDsEddie Hung2019-02-111-1/+1
| * | | | Do not ignore newline after AND in binary AIGEddie Hung2019-02-111-1/+0
* | | | | Use module->add{Not,And}Gate() functionsEddie Hung2019-02-121-8/+2
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* | | | Merge remote-tracking branch 'origin/dff_init' into read_aigerEddie Hung2019-02-082-7/+7
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| * | | Cope WIDTH of ff/latch cells is default of zeroEddie Hung2019-02-061-6/+6
| * | | Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
* | | | addDff -> addDffGate as per @daveshah1Eddie Hung2019-02-081-1/+1
* | | | Fix tabulationEddie Hung2019-02-081-28/+28
* | | | -module_name arg to go before -clk_nameEddie Hung2019-02-081-7/+7
* | | | Support and differentiate between ASCII and binary AIG testingEddie Hung2019-02-082-2/+6
* | | | Add missing "[options]" to read_blif helpEddie Hung2019-02-081-1/+1
* | | | Allow module name to be determined by argument tooEddie Hung2019-02-082-14/+44
* | | | Refactor into AigerReader classEddie Hung2019-02-082-79/+92
* | | | Parse binary AIG filesEddie Hung2019-02-081-49/+164
* | | | Add binary AIGs converted from AAGEddie Hung2019-02-0814-0/+51
* | | | Refactor to parse_aiger_header()Eddie Hung2019-02-081-26/+32
* | | | Add commentEddie Hung2019-02-081-0/+1
* | | | Handle reset logic in latchesEddie Hung2019-02-081-2/+17
* | | | Change literal vars from int to unsignedEddie Hung2019-02-081-1/+1
* | | | Create clk outside of latch loopEddie Hung2019-02-081-7/+9
* | | | Handle latch symbols tooEddie Hung2019-02-081-3/+1
* | | | Remove return after log_errorEddie Hung2019-02-081-27/+9
* | | | Add support for symbol tablesEddie Hung2019-02-081-1/+49
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