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abc9_map.v to transform INIT=1 to INIT=0
Eddie Hung
2019-12-04
2
-118
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+292
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Oh deary me
Eddie Hung
2019-12-04
1
-4
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+4
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Bump ABC to get "&verify -s" fix
Eddie Hung
2019-12-04
1
-1
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+1
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output reg Q -> output Q to suppress warning
Eddie Hung
2019-12-04
1
-8
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+8
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abc9_map.v to do `zinit' and make INIT = 1'b0
Eddie Hung
2019-12-04
1
-70
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+112
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Cleanup
Eddie Hung
2019-12-03
1
-11
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+12
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Add assertion
Eddie Hung
2019-12-03
1
-0
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+1
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write_xaiger to consume abc9_init attribute for abc9_flops
Eddie Hung
2019-12-03
1
-34
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+28
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Add abc9_init wire, attach to abc9_flop cell
Eddie Hung
2019-12-03
2
-4
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+24
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Revert "Add INIT value to abc9_control"
Eddie Hung
2019-12-03
1
-8
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+8
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Update ABCREV for upstream bugfix
Eddie Hung
2019-12-03
1
-1
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+1
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techmap abc_unmap.v before xilinx_srl -fixed
Eddie Hung
2019-12-03
1
-6
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+5
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Add INIT value to abc9_control
Eddie Hung
2019-12-02
1
-8
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+8
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Cleanup
Eddie Hung
2019-12-01
1
-3
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+2
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Use pool instead of std::set for determinism
Eddie Hung
2019-12-01
1
-1
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+1
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Use pool<> not std::set<> for determinism
Eddie Hung
2019-12-01
1
-4
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+4
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clkpart -unpart into 'finalize'
Eddie Hung
2019-11-28
1
-3
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+4
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-28
1
-1
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+1
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Move \init signal for non-port signals as long as internally driven
Eddie Hung
2019-11-28
1
-1
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+1
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
1
-0
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+31
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Fix multiple driver issue
Eddie Hung
2019-11-27
1
-2
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+7
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Add multiple driver testcase
Eddie Hung
2019-11-27
1
-0
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+31
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Fix multiple driver issue
Eddie Hung
2019-11-27
1
-2
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+7
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Add comment, use sigmap
Eddie Hung
2019-11-27
1
-2
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+2
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Revert "Fold loop"
Eddie Hung
2019-11-27
1
-3
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+6
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-27
5
-7
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+100
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Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
Eddie Hung
2019-11-27
2
-3
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+72
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No need for -abc9
Eddie Hung
2019-11-26
1
-1
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+1
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Add citation
Eddie Hung
2019-11-26
1
-0
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+1
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Check for either sign or zero extension for postAdd packing
Eddie Hung
2019-11-26
1
-3
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+3
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Add testcase derived from fastfir_dynamictaps benchmark
Eddie Hung
2019-11-26
1
-0
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+68
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Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
Clifford Wolf
2019-11-27
1
-0
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+4
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memory_collect: Copy attr from RTLIL::Memory to cell
David Shah
2019-11-18
1
-0
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+4
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Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
Clifford Wolf
2019-11-27
2
-4
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+24
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opt_share: Fix handling of fine cells.
Marcin Kościelnicki
2019-11-27
2
-4
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+24
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Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve
Eddie Hung
2019-11-27
2
-22
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+5
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ean call after abc{,9}
Eddie Hung
2019-11-27
1
-1
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+2
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
1
-7
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+3
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Do not replace constants with same wire
Eddie Hung
2019-11-27
1
-7
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+3
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Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Eddie Hung
2019-11-27
4
-34
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+30
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latch -> box
Eddie Hung
2019-11-26
1
-1
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+1
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Remove notes
Eddie Hung
2019-11-26
1
-9
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+0
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Fold loop
Eddie Hung
2019-11-26
1
-6
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+3
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Do not sigmap keep bits inside write_xaiger
Eddie Hung
2019-11-26
1
-1
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+1
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xaiger: do not promote output wires
Eddie Hung
2019-11-26
1
-5
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+0
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xilinx: Add simulation models for IOBUF and OBUFT.
Marcin Kościelnicki
2019-11-26
3
-25
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+30
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-27
0
-0
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+0
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clkpart to analyse async flops too
Eddie Hung
2019-11-25
1
-0
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+8
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
2
-49
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+94
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Cleanup
Eddie Hung
2019-11-27
1
-5
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+3
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