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author | Marcin KoĆcielnicki <mwk@0x04.net> | 2019-11-26 05:04:28 +0100 |
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committer | Marcin KoĆcielnicki <mwk@0x04.net> | 2019-11-26 08:15:20 +0100 |
commit | 0466c48533ad2831a95c6b63c3a190adb76499e9 (patch) | |
tree | bee4a2fbd4ebc5b0b16877057605b0ae145f2056 | |
parent | 6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d (diff) | |
download | yosys-0466c48533ad2831a95c6b63c3a190adb76499e9.tar.gz yosys-0466c48533ad2831a95c6b63c3a190adb76499e9.tar.bz2 yosys-0466c48533ad2831a95c6b63c3a190adb76499e9.zip |
xilinx: Add simulation models for IOBUF and OBUFT.
-rw-r--r-- | techlibs/xilinx/cells_sim.v | 28 | ||||
-rw-r--r-- | techlibs/xilinx/cells_xtra.py | 4 | ||||
-rw-r--r-- | techlibs/xilinx/cells_xtra.v | 23 |
3 files changed, 30 insertions, 25 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index fa33f4596..1be43f9d4 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -59,6 +59,34 @@ module OBUF( assign O = I; endmodule +module IOBUF ( + (* iopad_external_pin *) + inout IO, + output O, + input I, + input T +); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + assign IO = T ? 1'bz : I; + assign O = IO; +endmodule + +module OBUFT ( + (* iopad_external_pin *) + output O, + input I, + input T +); + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + assign O = T ? 1'bz : I; +endmodule + module BUFG( (* clkbuf_driver *) output O, diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index f401ebe78..82e403f78 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -326,7 +326,7 @@ CELLS = [ Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), # I/O. - Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), + # Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}), @@ -342,7 +342,7 @@ CELLS = [ Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), # Output + tristate. - Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), + # Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), # Pulls. Cell('KEEPER'), diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index ce0949f2c..671d16e8a 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -8160,18 +8160,6 @@ module IBUFGDS_DIFF_OUT (...); input IB; endmodule -module IOBUF (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - input I; - input T; -endmodule - module IOBUF_DCIEN (...); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; @@ -8373,17 +8361,6 @@ module OBUFDS_DPHY (...); input LPTX_T; endmodule -module OBUFT (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter integer DRIVE = 12; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - input I; - input T; -endmodule - module OBUFTDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter IOSTANDARD = "DEFAULT"; |