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| author | Clifford Wolf <clifford@clifford.at> | 2019-11-27 11:25:23 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-27 11:25:23 +0100 |
| commit | 41e0ddf4f4ac69b0c586b1c71e3ee200e1c892ce (patch) | |
| tree | 082c384a08e0755276902999062af2cc7aecf43f | |
| parent | f43c0bd8ba2a736b86504725429e25df27a29ac0 (diff) | |
| parent | 7ff5d6d30ae9f48376f0c6a98d8a5fa0831faf77 (diff) | |
| download | yosys-41e0ddf4f4ac69b0c586b1c71e3ee200e1c892ce.tar.gz yosys-41e0ddf4f4ac69b0c586b1c71e3ee200e1c892ce.tar.bz2 yosys-41e0ddf4f4ac69b0c586b1c71e3ee200e1c892ce.zip | |
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
memory_collect: Copy attr from RTLIL::Memory to cell
| -rw-r--r-- | passes/memory/memory_collect.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6acbce62f..9dcb3f024 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -218,6 +218,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) mem->setPort("\\RD_DATA", sig_rd_data); mem->setPort("\\RD_EN", sig_rd_en); + // Copy attributes from RTLIL memory to $mem + for (auto attr : memory->attributes) + mem->attributes[attr.first] = attr.second; + for (auto c : memcells) module->remove(c); |