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* Merge remote-tracking branch 'origin/eddie/script_from_wire' into xc7muxEddie Hung2019-06-283-8/+62
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| * Add to CHANGELOGEddie Hung2019-06-281-0/+6
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| * Support ability for "script -select" to take commands from wiresEddie Hung2019-06-281-8/+39
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| * Add testEddie Hung2019-06-281-0/+17
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* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-280-0/+0
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| * Replace log_assert() with meaningful log_error()Eddie Hung2019-06-281-1/+5
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| * Remove peepopt call in synth_xilinx since already in synth -run coarseEddie Hung2019-06-281-5/+0
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* | Restore $__XILINX_MUXF78 const optimisationEddie Hung2019-06-281-24/+24
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* | Clean up trimming leading 1'bx in A during techmappnigEddie Hung2019-06-281-15/+9
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* | Fix CARRY4 abc_box_idEddie Hung2019-06-281-1/+1
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* | Replace log_assert() with meaningful log_error()Eddie Hung2019-06-281-1/+5
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* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-281-0/+3
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| * Add missing CHANGELOG entriesEddie Hung2019-06-281-0/+3
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* | Update CHANGELOG with -widemuxEddie Hung2019-06-281-1/+1
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* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-280-0/+0
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| * Fix spacingEddie Hung2019-06-281-2/+2
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* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-2822-171/+335
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| * Merge pull request #1098 from YosysHQ/xaigEddie Hung2019-06-2845-247/+3642
| |\ | | | | | | "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
| | * Add generic __builtin_bswap32 functionEddie Hung2019-06-281-0/+15
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| | * Also fix write_aiger for UBEddie Hung2019-06-281-26/+26
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| | * Fix more potential for undefined behaviour due to container invalidationEddie Hung2019-06-281-6/+10
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| | * Update synth_ice40 -device doc to be relevant for -abc9 onlyEddie Hung2019-06-281-2/+2
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| | * Disable boxing of ECP5 dist RAM due to regressionEddie Hung2019-06-281-1/+1
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| | * Add write address to abc_scc_break of ECP5 dist RAMEddie Hung2019-06-281-1/+1
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| | * Fix DO4 typoEddie Hung2019-06-281-1/+1
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| | * Reduce diff with upstreamEddie Hung2019-06-271-4/+2
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| | * Extraneous newlineEddie Hung2019-06-271-1/+0
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| | * Remove noise from ice40/cells_sim.vEddie Hung2019-06-271-5/+0
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| | * Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-275-82/+84
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| | * Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-06-272-0/+19
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| | | * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-272-0/+19
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| | * | | Do not use Module::remove() iterator versionEddie Hung2019-06-271-5/+6
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| | * | | Remove redundant docEddie Hung2019-06-271-3/+0
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| | * | | Remove &retime when abc9 -fastEddie Hung2019-06-271-1/+1
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| | * | | Cleanup abc9.ccEddie Hung2019-06-271-15/+17
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| | * | | Undo iterator based Module::remove() for cells, as containers will notEddie Hung2019-06-272-11/+2
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| * | | Merge pull request #1146 from gsomlo/gls-test-abc-extClifford Wolf2019-06-284-8/+29
| |\ \ \ | | | | | | | | | | tests: use optional ABCEXTERNAL when specified
| | * | | tests: use optional ABCEXTERNAL when specifiedGabriel L. Somlo2019-06-274-8/+29
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commits 65924fd1, abc40924, and ebe29b66 hard-code the invocation of yosys-abc, which fails if ABCEXTERNAL was specified during the build. Allow tests to utilize an optional, externally specified abc binary. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
| * | | Merge pull request #1046 from bogdanvuk/masterClifford Wolf2019-06-285-16/+127
| |\ \ \ | | |/ / | |/| | Optimizing DFFs whose initial value prevents their value from changing
| | * | Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" tooBogdan Vukobratovic2019-06-272-2/+10
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| | * | Fix memory leak when one of multiple DFF cells is removed in opt_rmdffBogdan Vukobratovic2019-06-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | When there are multiple DFFs and one of them is removed, its reference lingers inside bit2driver dict. While invoking handle_dff() function for other DFFs, this broken reference is used isnside sat_import_cell() function.
| | * | Merge remote-tracking branch 'upstream/master'Bogdan Vukobratovic2019-06-2737-143/+1631
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| | * | | Refactor "opt_rmdff -sat"Clifford Wolf2019-06-204-373/+58
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Merge branch 'master' of https://github.com/bogdanvuk/yosys into ↵Clifford Wolf2019-06-205-10/+423
| | |\ \ \ | | | | | | | | | | | | | | | | | | clifford/ext1046
| | | * | | Move netlist helper module to passes/opt for the time beingBogdan Vukobratovic2019-06-142-1/+1
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| | | * | | Merge remote-tracking branch 'upstream/master'Bogdan Vukobratovic2019-06-1473-475/+1352
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| | | * | | | Prepare for situation when port of the signal cannot be foundBogdan Vukobratovic2019-06-142-2/+8
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| | | * | | | Some cleanup, revert sat.ccBogdan Vukobratovic2019-06-142-13/+11
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| | | * | | | Implement disconnection of constant register bitsBogdan Vukobratovic2019-06-132-44/+109
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| | | * | | | Pass SigBit by value to Netlist algorithmsBogdan Vukobratovic2019-06-131-65/+84
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