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* | Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-1519-47/+47
* | Removed old doc references to $safe_pmuxClifford Wolf2014-08-152-5/+1
* | More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-154-10/+22
* | Added Frontend "+/" filename syntax for files from proc_share_dirClifford Wolf2014-08-151-1/+4
* | document "techmap -map %<design-name>"Clifford Wolf2014-08-151-0/+3
* | Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-151-1/+1
* | Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-143-11/+20
* | Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-143-21/+31
* | Added sig.{replace,remove,extract} variants for std::{map,set} patternClifford Wolf2014-08-142-25/+64
* | Fixed line numbers when using here-doc macrosClifford Wolf2014-08-141-4/+9
* | Fixed handling of task outputsClifford Wolf2014-08-141-2/+4
* | Simplified $__arraymul techmap ruleClifford Wolf2014-08-141-7/+13
* | Added module->portsClifford Wolf2014-08-149-10/+23
* | Refactoring of CellType classClifford Wolf2014-08-143-155/+139
* | RIP $safe_pmuxClifford Wolf2014-08-1416-98/+21
* | Some improvements in FSM mapping and recodingClifford Wolf2014-08-143-9/+18
* | Added "abc -D" for setting delay targetClifford Wolf2014-08-141-5/+18
* | Updated ABC to 4935c2b946deClifford Wolf2014-08-141-1/+1
* | Added techmap support for actual lookahead carry unitClifford Wolf2014-08-131-22/+73
* | Preparations for lookahead ALU support in techmap.vClifford Wolf2014-08-131-28/+92
* | Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-131-0/+15
* | New interface for $__alu in techmap.vClifford Wolf2014-08-131-129/+62
* | Added support for non-standard """ macro bodiesClifford Wolf2014-08-132-1/+21
* | Fixed handling of constant-true branches in proc_cleanClifford Wolf2014-08-122-2/+3
* | Added test_verific mode to tests/fsm/generate.pyClifford Wolf2014-08-121-7/+17
* | Fixed SigBit(RTLIL::Wire *wire) constructorClifford Wolf2014-08-121-1/+1
* | Fixed building verific bindingsClifford Wolf2014-08-122-3/+3
* | Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-121-0/+11
* | Another build fix by americanrouter (via reddit)Clifford Wolf2014-08-111-0/+3
* | Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-102-8/+43
* | Fixed "share" for complex scenarios with never-active cellsClifford Wolf2014-08-091-6/+22
* | Do not share any $reduce_* cells (its complicated and not worth it anyways)Clifford Wolf2014-08-091-19/+0
* | Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-093-51/+103
* | Improved FSM testsClifford Wolf2014-08-084-2/+5
* | Another fsm_extract bugfixClifford Wolf2014-08-081-0/+4
* | Fixed "fsm -export"Clifford Wolf2014-08-082-6/+5
* | Fixed sharing of reduce operatorClifford Wolf2014-08-081-0/+13
* | Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-081-8/+25
* | Added FSM test benchClifford Wolf2014-08-082-0/+113
* | Added "sat -prove-skip"Clifford Wolf2014-08-081-2/+16
* | Fixed build with gcc-4.6Clifford Wolf2014-08-076-16/+24
* | Use "-keepdc" in "miter -equiv -flatten"Clifford Wolf2014-08-071-2/+2
* | Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-071-3/+5
* | Added adff2dff.v (for techmap -share_map)Clifford Wolf2014-08-072-1/+32
* | Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-065-6/+80
* | Various improvements in memory_dff passClifford Wolf2014-08-061-21/+22
* | Various fixes and improvements in wreduce passClifford Wolf2014-08-051-29/+47
* | Removed old "constmap" from wreduce codeClifford Wolf2014-08-051-3/+2
* | Added support for truncating of wires to wreduce passClifford Wolf2014-08-054-12/+93
* | Cleanups and improvements in wreduce passClifford Wolf2014-08-051-47/+77
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