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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-08 14:24:09 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-08 14:24:09 +0200 |
| commit | cb6ca08a53bfaa1b76798e6220bb1b267d49b235 (patch) | |
| tree | b1ffd2301e8ecc7d285d91fa3eb5be1a68c9d6ba | |
| parent | 7c94024fc32778cb6c789fc46a7bfbbcc7109e89 (diff) | |
| download | yosys-cb6ca08a53bfaa1b76798e6220bb1b267d49b235.tar.gz yosys-cb6ca08a53bfaa1b76798e6220bb1b267d49b235.tar.bz2 yosys-cb6ca08a53bfaa1b76798e6220bb1b267d49b235.zip | |
Fixed sharing of reduce operator
| -rw-r--r-- | passes/sat/share.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 0c88b4d3c..7141cea2a 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -252,6 +252,19 @@ struct ShareWorker if (config.generic_uni_ops.count(c1->type)) { + if (c1->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool") && c1->getParam("\\A_WIDTH").as_int() != c2->getParam("\\A_WIDTH").as_int()) + { + RTLIL::SigBit extbit = c1->type == "$reduce_and" ? RTLIL::State::S1 : RTLIL::State::S0; + while (c1->getParam("\\A_WIDTH").as_int() < c2->getParam("\\A_WIDTH").as_int()) { + c1->setParam("\\A_WIDTH", c1->getParam("\\A_WIDTH").as_int() + 1); + c1->setPort("\\A", {extbit, c1->getPort("\\A")}); + } + while (c2->getParam("\\A_WIDTH").as_int() < c1->getParam("\\A_WIDTH").as_int()) { + c2->setParam("\\A_WIDTH", c2->getParam("\\A_WIDTH").as_int() + 1); + c2->setPort("\\A", {extbit, c2->getPort("\\A")}); + } + } + if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; |