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* techmap: use C++11 default member initializers. NFC.whitequark2020-06-021-16/+6
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* techmap: simplify.whitequark2020-06-021-7/+1
| | | | `rewrite_filename` is already called in `Frontend::extra_args`.
* techmap: use +/techmap.v instead of an ad-hoc code generator.whitequark2020-06-023-16/+1
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* Merge pull request #2102 from YosysHQ/tests_fixclairexen2020-06-021-1/+2
|\ | | | | allow range for mux test
| * allow range for mux testMiodrag Milanovic2020-06-011-1/+2
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* | Merge pull request #2101 from YosysHQ/mmicko/verific_asymmetricclairexen2020-06-021-6/+1
|\ \ | |/ |/| Support asymmetric memories for verific frontend
| * Support asymmetric memories for verific frontendMiodrag Milanovic2020-06-011-6/+1
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* Merge pull request #1862 from boqwxp/cleanup_techmapclairexen2020-05-315-153/+169
|\ | | | | Clean up `passes/techmap/techmap.cc`
| * kernel: Try an order-independent approach to hashing `dict`.Alberto Gonzalez2020-05-191-5/+3
| | | | | | | | | | Co-Authored-By: David Shah <dave@ds0.me> Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * kernel: Ensure `dict` always hashes to the same value given the same contents.Alberto Gonzalez2020-05-141-3/+6
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| * kernel: Re-implement `dict` hash code as a `dict` member function instead of ↵Alberto Gonzalez2020-05-141-20/+14
| | | | | | | | a specialized template for `hash_ops`.
| * techmap: Replace naughty `const_cast<>()`s.Alberto Gonzalez2020-05-141-2/+4
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * techmap: Replace pseudo-private member usage with the range accessor ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | function and some naughty `const_cast<>()`s.
| * techmap: sort celltypeMap as it determines techmap orderEddie Hung2020-05-141-1/+5
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| * Replace `std::set`s using custom comparators with `pool`.Alberto Gonzalez2020-05-141-4/+4
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * techmap: prefix special wires with backslash for use as IdStringEddie Hung2020-05-143-12/+14
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| * Further clean up `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-5/+6
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * Use `emplace()` for more efficient insertion into various `dict`s.Alberto Gonzalez2020-05-141-8/+8
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| * Build constant bits directly rather than constructing an object and copying ↵Alberto Gonzalez2020-05-141-2/+5
| | | | | | | | its bits.
| * Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.Alberto Gonzalez2020-05-141-2/+2
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| * Use `emplace()` rather than `insert()`.Alberto Gonzalez2020-05-141-1/+1
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| * Clean up pseudo-private member usage and ensure range iteration uses ↵Alberto Gonzalez2020-05-141-17/+17
| | | | | | | | references where possible to avoid unnecessary copies.
| * Clean up extraneous buffer.Alberto Gonzalez2020-05-141-5/+2
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| * Replace `std::map` with `dict` for `unique_bit_id`.Alberto Gonzalez2020-05-141-1/+1
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| * Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | `cellbits_to_tplbits`.
| * Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | `outbit_to_cell`.
| * Replace `std::map` with `dict` for `TechmapWires` type.Alberto Gonzalez2020-05-141-1/+1
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| * Replace `std::map` with `dict` for `celltypeMap`.Alberto Gonzalez2020-05-141-3/+3
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| * Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.Alberto Gonzalez2020-05-141-4/+4
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| * Replace `std::map` with `dict` for `positional_ports`.Alberto Gonzalez2020-05-141-1/+1
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| * Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵Alberto Gonzalez2020-05-143-10/+25
| | | | | | | | `std::map` for `techmap_cache` and `techmap_do_cache`.
| * Replace `std::map` with `dict` for `simplemap_mappers`.Alberto Gonzalez2020-05-143-5/+5
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| * Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-10/+10
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| * Replace `std::string` and `RTLIL::IdString` with `IdString` in ↵Alberto Gonzalez2020-05-141-21/+21
| | | | | | | | | | | | `passes/techmap/techmap.cc`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * Do not modify design modules while iterating over `modules()`.Alberto Gonzalez2020-05-141-1/+4
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * Clean up pseudo-private member usage, superfluous `std::vector` ↵Alberto Gonzalez2020-05-141-76/+70
| | | | | | | | instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
* | Merge pull request #2081 from YosysHQ/eddie/blackbox_astEddie Hung2020-05-301-25/+1
|\ \ | | | | | | blackbox: use Module::makeblackbox() method
| * | blackbox: re-use existing Module::makeblackbox() methodEddie Hung2020-05-251-25/+1
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* | | Merge pull request #2018 from boqwxp/qbfsat-timeoutclairexen2020-05-303-18/+84
|\ \ \ | | | | | | | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
| * | | smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.Alberto Gonzalez2020-05-291-4/+0
| | | | | | | | | | | | | | | | Co-Authored-By: clairexen <claire@symbioticeda.com>
| * | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, ↵Alberto Gonzalez2020-05-253-18/+88
| | | | | | | | | | | | | | | | and CVC4.
* | | | Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logicclairexen2020-05-293-2/+11
|\ \ \ \ | | | | | | | | | | ast/simplify: don't bitblast async ROMs declared as `logic`
| * | | | ast/simplify: don't bitblast async ROMs declared as `logic`.whitequark2020-05-053-2/+11
| | | | | | | | | | | | | | | | | | | | Fixes #2020.
* | | | | Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-2926-40/+540
|\ \ \ \ \ | | | | | | | | | | | | Fix modulo/remainder semantics
| * | | | | Document division and modulo cellsXiretza2020-05-281-0/+23
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| * | | | | Update CHANGELOGXiretza2020-05-281-0/+1
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| * | | | | Add comments for mod/div semantics to rtlil.hXiretza2020-05-281-0/+4
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| * | | | | Expand tests/simple/constmuldivmod.vXiretza2020-05-281-1/+41
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| * | | | | Add flooring division operatorXiretza2020-05-2819-24/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
| * | | | | Add flooring modulo operatorXiretza2020-05-2823-37/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
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