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* Leftover printfEddie Hung2019-03-221-1/+0
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* Fixes for multibitEddie Hung2019-03-221-18/+38
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* Working for 1 bitEddie Hung2019-03-221-11/+49
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* Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-227-44/+115
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| * Merge pull request #889 from YosysHQ/clifford/fix888Clifford Wolf2019-03-221-1/+10
| |\ | | | | | | Fix mem2reg handling of memories with upto data ports
| | * Fix mem2reg handling of memories with upto data ports, fixes #888Clifford Wolf2019-03-211-1/+10
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #890 from YosysHQ/clifford/fix887Clifford Wolf2019-03-221-1/+26
| |\ \ | | | | | | | | Trim init attributes when resizing FFs in "wreduce"
| | * | Trim init attributes when resizing FFs in "wreduce", fixes #887Clifford Wolf2019-03-221-1/+26
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #891 from YosysHQ/xilinx_keepDavid Shah2019-03-222-25/+31
| |\ \ | | |/ | |/| xilinx: Add keep attribute where appropriate
| | * xilinx: Add keep attribute where appropriateDavid Shah2019-03-222-25/+31
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * Improve "read_verilog -dump_vlog[12]" handling of upto rangesClifford Wolf2019-03-211-3/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve read_verilog debug output capabilitiesClifford Wolf2019-03-213-15/+42
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
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* | OptEddie Hung2019-03-211-1/+1
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* | Fix spacingEddie Hung2019-03-201-239/+239
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* | Fine tune cells_map.vEddie Hung2019-03-201-19/+15
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* | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable lengthEddie Hung2019-03-192-58/+34
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* | Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-192-17/+67
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* | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
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* | Fix spacingEddie Hung2019-03-191-1/+1
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* | shregmap -tech xilinx to delete $shiftx for var length SRLEddie Hung2019-03-191-10/+3
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* | Fix INIT for variable length SRs that have been bumped up oneEddie Hung2019-03-191-1/+1
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* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-1953-38/+2398
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| * Merge pull request #885 from YosysHQ/clifford/fix873Clifford Wolf2019-03-191-2/+4
| |\ | | | | | | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
| | * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #808 from eddiehung/read_aigerEddie Hung2019-03-1935-6/+632
| |\ | | | | | | Add new read_aiger frontend
| | * Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-19113-792/+6364
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| * | Merge pull request #884 from zachjs/masterClifford Wolf2019-03-192-1/+61
| |\ \ | | | | | | | | fix local name resolution in prefix constructs
| | * | fix local name resolution in prefix constructsZachary Snow2019-03-182-1/+61
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| * | Update issue templateClifford Wolf2019-03-171-5/+5
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Update issue templateClifford Wolf2019-03-171-0/+8
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #877 from FelixVi/masterClifford Wolf2019-03-161-1/+4
| |\ \ | | | | | | | | Add note about test requirements in README
| | * | Add note about test requirements in READMEFelix Vietmeyer2019-03-161-1/+4
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| * | Improve mix of src/wire/wirebit coverage in "mutate -list"Clifford Wolf2019-03-161-29/+84
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #876 from YosysHQ/clifford/fmcombineClifford Wolf2019-03-164-17/+374
| |\ \ | | | | | | | | Add fmcombine pass
| | * | Add "fmcombine -fwd -bwd -nop"Clifford Wolf2019-03-151-10/+59
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add fmcombine passClifford Wolf2019-03-154-17/+325
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #875 from YosysHQ/clifford/mutateClifford Wolf2019-03-154-5/+862
| |\ \ | | | | | | | | Add "mutate" pass
| | * | Improvements in "mutate" list-reduce algorithmClifford Wolf2019-03-151-13/+36
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add "mutate -cfg", improve pick_cover behaviorClifford Wolf2019-03-141-46/+101
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add a strictly coverage-driven mutation selection strategyClifford Wolf2019-03-141-1/+70
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Improve "mutate" wire coverage metricClifford Wolf2019-03-141-1/+16
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add more mutation types, improve mutation src coverClifford Wolf2019-03-141-92/+268
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Fix smtbmc.py handling of zero appended stepsClifford Wolf2019-03-141-5/+5
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add "mutate" command DB reduce functionalityClifford Wolf2019-03-141-12/+181
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add hashlib "<container>::element(int n)" methodsClifford Wolf2019-03-141-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add "mutate -mode inv", various other mutate improvementsClifford Wolf2019-03-141-99/+213
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add basic "mutate -list N" frameworkClifford Wolf2019-03-142-0/+230
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Disable realmath testsClifford Wolf2019-03-151-1/+1
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #874 from YosysHQ/clifford/andoptClifford Wolf2019-03-141-0/+7
| |\ \ | | | | | | | | Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
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