| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
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| | | * | | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 | |
| | | * | | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 | |
| | | * | | | | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
| | | * | | | | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 | |
| | | * | | | | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 | |
| | | * | | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 | |
| | | * | | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 58 | -598/+1321 | |
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| | | * | | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 | |
| | | * | | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 | |
| | | * | | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 | |
| | | * | | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 | |
| * | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 1 | -1/+1 | |
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| | * | | | | | | Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg | Clifford Wolf | 2019-08-22 | 2 | -0/+17 | |
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| | * \ \ \ \ \ \ | Merge pull request #1315 from mmicko/fix_dependencies | whitequark | 2019-08-21 | 1 | -1/+1 | |
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| | | * | | | | | | Fix test_pmgen deps | Miodrag Milanovic | 2019-08-21 | 1 | -1/+1 | |
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| * | | | | | | | Reuse var | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
| * | | | | | | | Revert "Trim shiftx_width when upper bits are 1'bx" | Eddie Hung | 2019-08-21 | 1 | -6/+1 | |
| * | | | | | | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 | |
| * | | | | | | | Trim shiftx_width when upper bits are 1'bx | Eddie Hung | 2019-08-21 | 1 | -1/+6 | |
| * | | | | | | | Add comment | Eddie Hung | 2019-08-21 | 1 | -0/+4 | |
| * | | | | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -18/+167 | |
| * | | | | | | | Rename pattern to fixed | Eddie Hung | 2019-08-21 | 2 | -10/+10 | |
| * | | | | | | | attribute -> attr | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
| * | | | | | | | Use Cell::has_keep_attribute() | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
| * | | | | | | | abc9 to perform new 'map_ffs' before 'map_luts' | Eddie Hung | 2019-08-21 | 1 | -3/+18 | |
| * | | | | | | | xilinx_srl to support FDRE and FDRE_1 | Eddie Hung | 2019-08-21 | 2 | -10/+73 | |
| * | | | | | | | Fix polarity of EN_POL | Eddie Hung | 2019-08-21 | 1 | -2/+2 | |
| * | | | | | | | Add CLKPOL == 0 | Eddie Hung | 2019-08-21 | 1 | -0/+2 | |
| * | | | | | | | Reject if not minlen from inside pattern matcher | Eddie Hung | 2019-08-21 | 2 | -8/+11 | |
| * | | | | | | | Get wire via SigBit | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
| * | | | | | | | Respect \keep on cells or wires | Eddie Hung | 2019-08-21 | 1 | -2/+10 | |
| * | | | | | | | Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl | Eddie Hung | 2019-08-21 | 2 | -0/+17 | |
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| | * | | | | | | mem2reg to preserve user attributes and src | Eddie Hung | 2019-08-21 | 2 | -0/+17 | |
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| * | | | | | | Add init support | Eddie Hung | 2019-08-21 | 2 | -3/+12 | |
| * | | | | | | Fix spacing | Eddie Hung | 2019-08-21 | 1 | -2/+2 | |
| * | | | | | | Initial progress on xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -0/+213 | |
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| * | | | | | Merge pull request #1314 from YosysHQ/eddie/fix_techmap | Clifford Wolf | 2019-08-21 | 4 | -4/+21 | |
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| | * | | | | | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
| | * | | | | | Add test | Eddie Hung | 2019-08-20 | 3 | -0/+15 | |
| | * | | | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 | |
| * | | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
| * | | | | | | Fix copy-paste typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 5 | -16/+23 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 191 | -4502/+7003 | |
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| | * | | | | | | Bump abc to fix &mfs bug | Eddie Hung | 2019-07-25 | 1 | -1/+1 | |
| | * | | | | | | Update changelog | Eddie Hung | 2019-07-22 | 1 | -3/+4 | |
| | * | | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
| | * | | | | | | Add CHANGELOG entry | Eddie Hung | 2019-07-18 | 1 | -0/+3 | |
| | * | | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 | |
| * | | | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 6 | -104/+138 | |
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