| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | xilinx_srl now copes with word-level flops $dff{,e} | Eddie Hung | 2019-08-23 | 1 | -8/+3 |
| * | xilinx_srl to use 'slice' features of pmgen for word level | Eddie Hung | 2019-08-23 | 2 | -32/+49 |
| * | Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 5 | -34/+280 |
| |\ |
|
| | * | Fix port hanlding in pmgen | Clifford Wolf | 2019-08-23 | 1 | -4/+3 |
| | * | Add pmgen slices and choices | Clifford Wolf | 2019-08-23 | 5 | -28/+277 |
| * | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 9 | -20/+43 |
| |\ \ |
|
| | * | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
| | * | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 3 | -14/+28 |
| | * | | Merge pull request #1326 from mmicko/doc-update | Eddie Hung | 2019-08-23 | 1 | -2/+5 |
| | |\ \
| | |/
| |/| |
|
| | | * | Make macOS depenency clear | Miodrag Milanovic | 2019-08-23 | 1 | -2/+5 |
| | |/ |
|
| | * | Do not propagate mem2reg attribute through to result | Eddie Hung | 2019-08-22 | 2 | -1/+3 |
| | * | Spelling | Eddie Hung | 2019-08-22 | 1 | -2/+2 |
| | * | Merge pull request #1322 from mmicko/pyosys_osx | Eddie Hung | 2019-08-22 | 1 | -0/+2 |
| | |\ |
|
| | | * | do not require boost if pyosys is not used | Miodrag Milanovic | 2019-08-22 | 1 | -0/+2 |
| | |/ |
|
| | * | Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
| | |\ |
|
| | | * | require tcl-tk in Brewfile | Chris Shucksmith | 2019-08-22 | 1 | -0/+1 |
| * | | | In sat: 'x' in init attr should not override constant | Eddie Hung | 2019-08-22 | 3 | -1/+7 |
| * | | | Remove Xilinx test | Eddie Hung | 2019-08-22 | 1 | -34/+0 |
| * | | | Actually, there might not be any harm in updating sigmap... | Eddie Hung | 2019-08-22 | 1 | -3/+1 |
| * | | | Add comment as per @cliffordwolf | Eddie Hung | 2019-08-22 | 1 | -0/+11 |
| * | | | Add shregmap -tech xilinx test | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
| * | | | Revert "Try way that doesn't involve creating a new wire" | Eddie Hung | 2019-08-22 | 1 | -15/+10 |
| * | | | Try way that doesn't involve creating a new wire | Eddie Hung | 2019-08-22 | 1 | -10/+15 |
| * | | | If d_bit already in sigbit_chain_next, create extra wire | Eddie Hung | 2019-08-22 | 1 | -3/+6 |
| * | | | Add doc | Eddie Hung | 2019-08-22 | 1 | -1/+14 |
| * | | | Add copyright | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
| * | | | Add CHANGELOG entry | Eddie Hung | 2019-08-22 | 1 | -0/+2 |
| * | | | Remove `shregmap -tech xilinx` additions | Eddie Hung | 2019-08-22 | 1 | -189/+8 |
| * | | | pmgen to also iterate over all module ports | Eddie Hung | 2019-08-22 | 1 | -2/+4 |
| * | | | Remove output_bits | Eddie Hung | 2019-08-22 | 2 | -16/+7 |
| * | | | Forgot to set ud_variable.minlen | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
| * | | | Do not run xilinx_srl_pm in fixed loop | Eddie Hung | 2019-08-22 | 1 | -28/+24 |
| * | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 19 | -102/+1046 |
| |\| | |
|
| | * | | Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx | Eddie Hung | 2019-08-22 | 2 | -4/+96 |
| | |\ \ |
|
| | | * | | Copy-paste typo | Eddie Hung | 2019-08-22 | 1 | -1/+1 |
| | | * | | Respect opt_expr -keepdc as per @cliffordwolf | Eddie Hung | 2019-08-22 | 2 | -1/+15 |
| | | * | | Handle $shift and Y_WIDTH > 1 as per @cliffordwolf | Eddie Hung | 2019-08-22 | 2 | -5/+51 |
| | | * | | Add cover() | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
| | | * | | Canonical form | Eddie Hung | 2019-08-22 | 1 | -5/+5 |
| | | * | | Add test | Eddie Hung | 2019-08-21 | 1 | -0/+14 |
| | | * | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 |
| | * | | | Bump year in copyright notice | Clifford Wolf | 2019-08-22 | 3 | -3/+3 |
| | * | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | * | | | Merge pull request #1289 from mmicko/anlogic_fixes | Clifford Wolf | 2019-08-22 | 5 | -91/+162 |
| | |\ \ \ |
|
| | | * \ \ | Merge remote-tracking branch 'upstream/master' into anlogic_fixes | Miodrag Milanovic | 2019-08-18 | 109 | -3621/+4745 |
| | | |\ \ \ |
|
| | | * | | | | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 5 | -91/+162 |
| | * | | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | * | | | | | Merge pull request #1281 from mmicko/efinix | Clifford Wolf | 2019-08-22 | 9 | -0/+798 |
| | |\ \ \ \ \
| | |_|_|_|/
| |/| | | | |
|
| | | * | | | | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
| | | * | | | | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 |
