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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-11 08:37:56 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-11 08:37:56 +0200 |
| commit | b3a91d6508943c8e5656af0a624e6ad115aec9c3 (patch) | |
| tree | 377cb07dd4221372a33c701a60d16ea892a56ddd | |
| parent | d51b135e331326032b003934905c17750e116014 (diff) | |
| download | yosys-b3a91d6508943c8e5656af0a624e6ad115aec9c3.tar.gz yosys-b3a91d6508943c8e5656af0a624e6ad115aec9c3.tar.bz2 yosys-b3a91d6508943c8e5656af0a624e6ad115aec9c3.zip | |
cleanup
| -rw-r--r-- | techlibs/efinix/arith_map.v | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v index ef903171f..56e1b039f 100644 --- a/techlibs/efinix/arith_map.v +++ b/techlibs/efinix/arith_map.v @@ -32,6 +32,9 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); input CI, BI; output [Y_WIDTH-1:0] CO; + + wire CIx; + wire [Y_WIDTH-1:0] COx; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; @@ -41,14 +44,14 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - wire [Y_WIDTH:0] C; + wire [Y_WIDTH-1:0] C = { COx, CIx }; EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) adder_cin ( .I0(CI), .I1(1'b1), .CI(1'b0), - .CO(C[0]) + .CO(CIx) ); genvar i; @@ -59,13 +62,13 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); .I1(BB[i]), .CI(C[i]), .O(Y[i]), - .CO(C[i+1]) + .CO(COx[i]) ); EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) adder_cout ( .I0(1'b0), .I1(1'b0), - .CI(C[i+1]), + .CI(COx[i]), .O(CO[i]) ); end: slice |