aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorEddie Hung <eddie@fpgeh.com>2019-08-23 12:22:46 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-23 12:22:46 -0700
commit08139aa53ab2aa7916c9c42fab9bf6261621c265 (patch)
tree6a336729b5eca78ab27ecda8ec6cf2fb857199be
parent18b64609c25313c73ac18af1c5963bf830f95dba (diff)
downloadyosys-08139aa53ab2aa7916c9c42fab9bf6261621c265.tar.gz
yosys-08139aa53ab2aa7916c9c42fab9bf6261621c265.tar.bz2
yosys-08139aa53ab2aa7916c9c42fab9bf6261621c265.zip
xilinx_srl now copes with word-level flops $dff{,e}
-rw-r--r--techlibs/xilinx/synth_xilinx.cc11
1 files changed, 3 insertions, 8 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 8bf43bf97..5e9cd8a0e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -265,9 +265,8 @@ struct SynthXilinxPass : public ScriptPass
if (widemux > 0 || help_mode)
run("muxpack", " ('-widemux' only)");
- // shregmap -tech xilinx can cope with $shiftx and $mux
- // cells for identifying variable-length shift registers,
- // so attempt to convert $pmux-es to the former
+ // xilinx_srl looks for $shiftx cells for identifying variable-length
+ // shift registers, so attempt to convert $pmux-es to this
// Also: wide multiplexer inference benefits from this too
if (!(nosrl && widemux == 0) || help_mode) {
run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
@@ -349,12 +348,8 @@ struct SynthXilinxPass : public ScriptPass
}
run("opt -full");
- if (!nosrl || help_mode) {
- // shregmap operates on bit-level flops, not word-level,
- // so break those down here
- run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
+ if (!nosrl || help_mode)
run("xilinx_srl -variable -minlen 3", "(skip if '-nosrl')");
- }
std::string techmap_args = " -map +/techmap.v";
if (help_mode)