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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 15:46:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 15:46:58 -0700 |
| commit | 6d76ae4c65d3a7b403888219900a3c0f85ee737d (patch) | |
| tree | e530f08c4e79d265aaf6575dbb3e730a3ef465a6 | |
| parent | b0a3b430bf1a54b00daf9a33818598057f67cf7c (diff) | |
| download | yosys-6d76ae4c65d3a7b403888219900a3c0f85ee737d.tar.gz yosys-6d76ae4c65d3a7b403888219900a3c0f85ee737d.tar.bz2 yosys-6d76ae4c65d3a7b403888219900a3c0f85ee737d.zip | |
Rename pattern to fixed
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 18 | ||||
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 2 |
2 files changed, 10 insertions, 10 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 862b44bb0..029cb3235 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -30,10 +30,10 @@ bool did_something; #include "passes/pmgen/ice40_dsp_pm.h" #include "passes/pmgen/peepopt_pm.h" -void reduce_chain(xilinx_srl_pm &pm) +void fixed(xilinx_srl_pm &pm) { - auto &st = pm.st_reduce; - auto &ud = pm.ud_reduce; + auto &st = pm.st_fixed; + auto &ud = pm.ud_fixed; auto param_def = [&ud](Cell *cell, IdString param) { auto def = ud.default_params.at(std::make_pair(cell->type,param)); return cell->parameters.at(param, def); @@ -130,13 +130,13 @@ struct XilinxSrlPass : public Pass { bool did_something = false; do { auto pm = xilinx_srl_pm(module, module->selected_cells()); - pm.ud_reduce.minlen = minlen; + pm.ud_fixed.minlen = minlen; // TODO: How to get these automatically? - pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; - pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; - pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; - pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; - did_something = pm.run_reduce(reduce_chain); + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; + did_something = pm.run_fixed(fixed); } while (did_something); } } diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 6c740b7a7..e7086c424 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -1,4 +1,4 @@ -pattern reduce +pattern fixed udata <vector<Cell*>> chain longest_chain udata <pool<Cell*>> non_first_cells |