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* cmake: Make HeAP placer always-enabledgatecat2023-03-171-10/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Check IO-bank compatibilitygatecat2023-02-211-0/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add missing <set> includesgatecat2023-01-202-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: add explain_invalid option to isBelLocationValidgatecat2022-12-072-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-072-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-021-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Transform registered output parametersDavid Lattimore2022-10-052-0/+9
| | | | | | | | | | | | Dual ported: OUTREG_A -> OUT_REGMODE_A OUTREG_B -> OUT_REGMODE_B Pseudo dual ported: OUTREG -> OUT_REGMODE_B Single ported: OUTREG -> OUT_REGMODE_A
* Merge pull request #1019 from antmicro/support-clock-relationsmyrtle2022-09-201-4/+11
|\ | | | | Support cross-domain clock relations in timing analyser
| * Code cleanupMaciej Kurc2022-08-311-4/+4
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Fixed port timing classes of DCC ports in the Nexus architectureMaciej Kurc2022-08-301-4/+11
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | nexus: Add ES2 device names and --list-devicesgatecat2022-09-153-1/+42
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use IdString::in instead of || chainsgatecat2022-08-105-28/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Add timing data for LRAMgatecat2022-08-103-0/+30
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-103-34/+31
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix CSDECODE parsinggatecat2022-07-191-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Change write_dcc to work with tilegroups from prjoxideMaciej Dudek2022-05-271-3/+2
| | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* clangformatgatecat2022-03-313-12/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Rename parse_lattice_param to parse_lattice_param_from_cellMaciej Dudek2022-03-303-36/+46
| | | | | | | | | Add new definition for parse_lattice_param Now parse_lattice_param is design to parse Property rather than search for it in cell. This functionalty was move to parse_lattice_param_from_cell. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* Nexus: Fixed OSCA parameters, add pll default parametersMaciej Dudek2022-03-181-2/+142
| | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* clangformatgatecat2022-03-172-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Corrected auto frequency constraint for LF output of OSCAMaciej Kurc2022-03-161-2/+2
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* nexus: Added support for the DCS BelMaciej Kurc2022-03-165-3/+57
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* nexus: Added FASM feature emission for DCC and port timing class infoMaciej Kurc2022-03-152-0/+20
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* clangformatgatecat2022-03-091-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: DCCs cannot be cascadedMaciej Dudek2022-03-091-1/+1
| | | | | | This commit solves implicit cascading when clock signal drives DCC and logic Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* Switch to potentially-sparse net users arraygatecat2022-02-272-24/+27
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-183-163/+163
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-165-44/+65
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: reduce OSCA worst case to 7%Dan Callaghan2022-02-101-1/+1
| | | | | | | | | | | The current version of Crosslink-NX Family Data Sheet lists the high frequency oscillator maximum frequency as 481.5MHz (that is, 7% higher than its nominal 450MHz): https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/CrossLink/FPGA-DS-02049-1-2-1-CrossLink-NX-Family.ashx?document_id=52780 Older documents listed a wider frequency range but ±7% is the range for production parts.
* Merge pull request #905 from YosysHQ/gatecat/nexus-disable-dcsroutegatecat2022-02-031-1/+6
|\ | | | | nexus: Hotfix to disable unimplemented DCS routethru
| * nexus: Hotfix to disable unimplemented DCS routethrugatecat2022-02-031-1/+6
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | run clangformatgatecat2022-02-031-2/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixed correction of Nexus OSCA frequency constraintsMaciej Kurc2022-02-021-2/+2
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* nexus: add option to modify the mult factor of the estimate delayAlessandro Comodi2022-02-013-1/+11
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Added honoring OSCA output frequency tolerance during constraints generationMaciej Kurc2022-01-281-2/+3
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Removed the need for MULT36_CORE bel for implementing the MULTADDSUB9X9WIDE ↵Maciej Kurc2022-01-251-1/+1
| | | | | | macro Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* nexus: handle SLEWRATE in pdcKarol Gugala2021-12-203-2/+10
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* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-8/+6
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: router1 speedup based on #867gatecat2021-12-172-2/+73
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-12-122-16/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Added checking if all FFs added to an existing cluster have matching ↵Maciej Kurc2021-11-231-0/+44
| | | | | | configuration Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Fixed potential issues with carry-chain cluster expansion, added a parameter ↵Maciej Kurc2021-11-222-14/+23
| | | | | | controlling the ratio of FFs that got glued to carry-chain clusters. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added appending FFs to other existing LUT cluster types (carry, widefn)Maciej Kurc2021-11-221-18/+67
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added an option to control LUT and FF packingMaciej Kurc2021-11-222-1/+8
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added clustering free LUTs and FFsMaciej Kurc2021-11-221-0/+73
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* nexus: Add resource cost overridesgatecat2021-09-242-2/+21
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: LUT permutation supportgatecat2021-09-244-4/+72
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #822 from YosysHQ/gatecat/nexus-split-vccgatecat2021-09-233-0/+7
|\ | | | | nexus: Support for split Vcc routing
| * nexus: Support for split Vcc routinggatecat2021-09-223-0/+7
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #823 from YosysHQ/gatecat/nexus-r1-tweaksgatecat2021-09-222-2/+4
|\ \ | | | | | | nexus: Tweaks for router1 performance
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