diff options
| author | gatecat <gatecat@ds0.me> | 2021-09-22 14:10:20 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-09-22 15:00:59 +0100 |
| commit | f395ad3e27bf5453f7a5393e9039988f44215cec (patch) | |
| tree | 7a65cb001be566363ffba006fc36410e70de9bbf /nexus | |
| parent | 035452d938a6ba005ecc7ee9bd308879eaff6069 (diff) | |
| download | nextpnr-f395ad3e27bf5453f7a5393e9039988f44215cec.tar.gz nextpnr-f395ad3e27bf5453f7a5393e9039988f44215cec.tar.bz2 nextpnr-f395ad3e27bf5453f7a5393e9039988f44215cec.zip | |
nexus: Support for split Vcc routing
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'nexus')
| -rw-r--r-- | nexus/arch.cc | 3 | ||||
| -rw-r--r-- | nexus/constids.inc | 2 | ||||
| -rw-r--r-- | nexus/fasm.cc | 2 |
3 files changed, 7 insertions, 0 deletions
diff --git a/nexus/arch.cc b/nexus/arch.cc index f3430968..1b98a365 100644 --- a/nexus/arch.cc +++ b/nexus/arch.cc @@ -589,6 +589,9 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port delay_t Arch::estimateDelay(WireId src, WireId dst) const { + const auto &dst_data = wire_data(dst); + if (src.tile == 0 && dst_data.name == ID_LOCAL_VCC) + return 0; int src_x = src.tile % chip_info->width, src_y = src.tile / chip_info->width; int dst_x = dst.tile % chip_info->width, dst_y = dst.tile / chip_info->width; int dist_x = std::abs(src_x - dst_x); diff --git a/nexus/constids.inc b/nexus/constids.inc index 5407cb23..48b0ca2b 100644 --- a/nexus/constids.inc +++ b/nexus/constids.inc @@ -528,3 +528,5 @@ X(TOUT) X(Q0) X(Q1) X(SCLK) + +X(LOCAL_VCC) diff --git a/nexus/fasm.cc b/nexus/fasm.cc index c4eb9a1b..964828cb 100644 --- a/nexus/fasm.cc +++ b/nexus/fasm.cc @@ -211,6 +211,8 @@ struct NexusFasmWriter return; std::string tile = tile_name(pip.tile, tile_by_type_and_loc(pip.tile, IdString(pd.tile_type))); std::string source_wire = escape_name(ctx->pip_src_wire_name(pip).str(ctx)); + if (source_wire == "LOCAL_VCC") + source_wire = "G__VCC"; std::string dest_wire = escape_name(ctx->pip_dst_wire_name(pip).str(ctx)); out << stringf("%s.PIP.%s.%s", tile.c_str(), dest_wire.c_str(), source_wire.c_str()) << std::endl; } |