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* move submodules to localHEADmasterroot2023-05-021-2/+2
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* gowin: fix styleYRabbit2023-04-201-16/+16
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: fix styleYRabbit2023-04-201-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add a common mechanism for placing portsYRabbit2023-04-202-53/+35
| | | | | | | If the port is in a different cell than the primitive, then use the alias mechanism. Considerably compact code for OSC as an example. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove inherited code for ODDR(c)YRabbit2023-04-144-153/+40
| | | | | | | Implement ODDR(c) as part of IOLOGIC and remove all old code associated with those primitives. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* fabulous: Support for configurable LUT sizegatecat2023-04-132-2/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Fix styleYRabbit2023-04-121-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: implement IDES16 and OSER16 primitivesYRabbit2023-04-125-19/+454
| | | | | | | | | These are very cumbersome primitives that take up two cells and consequently 4 IOLOGIC bels. The primitives are implemented for the chips that contain them and are supported by apicula GW1NSR-4C, GW1NR-9 and GW1NR-9C. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* ecp5: Fix invalid accesses during certain IO packing casesgatecat2023-04-121-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* viaduct: Add support for GUIsgatecat2023-04-1111-61/+135
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Add implementation of IDDR and IDDRC primitivesYRabbit2023-04-062-17/+30
| | | | | | | | Simple deserialization primitives are implemented for all supported boards. Compatible with older apicula bases. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* fabulous: Fix bel names for pass bels in v2 formatgatecat2023-04-052-2/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Add support for IDES primitivesYRabbit2023-04-043-16/+159
| | | | | | | | | | | | * placement of IDES4, IVIDEO, IDES8 and IDES10 primitives is supported; * primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C, GW1NR-9, GW1NR-9C chips; * tricks required for IOLOGIC to work on one side of the -9 and -9C chips are taken into account; Compatible with old apicula bases. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: bugfixYRabbit2023-03-232-2/+3
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Rename questionable portsYRabbit2023-03-233-50/+50
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Change the way errors are processedYRabbit2023-03-231-4/+4
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add support for OSER primitivesYRabbit2023-03-236-40/+338
| | | | | | | | | | | | | | | | * placement of OSER4, OVIDEO, OSER8 and SER10 primitives is supported; * primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C, GW1NR-9, GW1NR-9C chips; * the initial support for special HCLK clock wires is implemented to the extent necessary for OSER primitives to function; * output to both regular IO and TLVDS_OBUF is supported; * tricks required for IOLOGIC to work on one side of the -9 and -9C chips are taken into account; * various edits, such as using idf() instead of the local buffer. Compatible with old apicula bases. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* ice40: Fix BRAM NegClk bitstream logicgatecat2023-03-201-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update prjtrellisMiodrag Milanovic2023-03-201-1/+1
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* Add ramaining PIO tilesMiodrag Milanovic2023-03-201-4/+11
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* Use unified io location dataMiodrag Milanovic2023-03-201-12/+2
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* Use TRELLIS primitivesMiodrag Milanovic2023-03-208-40/+39
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* Use RelSlice, make more in line with ecp5 archMiodrag Milanovic2023-03-204-146/+113
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* cmake: Make HeAP placer always-enabledgatecat2023-03-1712-107/+17
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2023-03-175-29/+29
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update prjtrellis to latestMiodrag Milanovic2023-03-161-1/+1
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* Update to latest prjtrellisMiodrag Milanovic2023-03-161-1/+1
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* Fix out of tree builds and place h in generatedMiodrag Milanovic2023-03-164-4/+4
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* Let top tiles be on topMiodrag Milanovic2023-03-161-3/+3
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* Enable wires and add dummy wire type for nowMiodrag Milanovic2023-03-165-7/+37
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* Basic GUI part selectionMiodrag Milanovic2023-03-163-23/+36
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* Fix examplesMiodrag Milanovic2023-03-165-6/+6
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* Extend chipdb with metadataMiodrag Milanovic2023-03-1611-216/+192
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* add new field handling in chip config formatMiodrag Milanovic2023-03-162-0/+4
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* Add simple BEL graphicsMiodrag Milanovic2023-03-165-1/+245
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* Make small GUI changesMiodrag Milanovic2023-03-166-14/+77
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* Expand list of possible devicesMiodrag Milanovic2023-03-162-4/+29
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* Remove anoying warning from cmakeMiodrag Milanovic2023-03-161-1/+2
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* ecp5: Update GUI rendering to match arch changesgatecat2023-03-161-25/+81
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2023-03-161-66/+42
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router1: Add error when dest port has no wiregatecat2023-03-061-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Misc improvementsgatecat2023-02-283-2/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Support for complex flops in PnRgatecat2023-02-284-4/+37
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Add python binding for write_bitstreamgatecat2023-02-281-0/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Add timing model for carriesgatecat2023-02-271-0/+20
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: LUT permutation supportgatecat2023-02-274-2/+102
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Global constant wires schemegatecat2023-02-236-15/+140
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* CMake: detect platform support for threadsCatherine2023-02-231-14/+13
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* common: disable parallel refinement only without threads.Catherine2023-02-235-9/+9
| | | | Previously it was always disabled on WebAssembly builds.
* common: update deprecated use of `boost::filesystem::basename`.Catherine2023-02-231-2/+2
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