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authorgatecat <gatecat@ds0.me>2022-03-31 10:49:00 +0100
committergatecat <gatecat@ds0.me>2022-03-31 10:49:00 +0100
commit2ed68a21db9d04e5688c4c0784b0817f3485926e (patch)
treeffb8bca0933afaee3bc906712b0f3f91fc41b625 /nexus
parent219310b20387a0dd781d4c1b587d04be99148a34 (diff)
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clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'nexus')
-rw-r--r--nexus/arch.h2
-rw-r--r--nexus/fasm.cc17
-rw-r--r--nexus/pack.cc5
3 files changed, 12 insertions, 12 deletions
diff --git a/nexus/arch.h b/nexus/arch.h
index 323dcacd..d713afcf 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1409,7 +1409,7 @@ struct Arch : BaseArch<ArchRanges>
// Parse a possibly-Lattice-style (C literal in Verilog string) style parameter
Property parse_lattice_param_from_cell(const CellInfo *ci, IdString prop, int width, int64_t defval) const;
- Property parse_lattice_param(const Property &val, IdString prop, int width, const char* ci="") const;
+ Property parse_lattice_param(const Property &val, IdString prop, int width, const char *ci = "") const;
// -------------------------------------------------
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index a6e94d73..3ed5785e 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -523,7 +523,8 @@ struct NexusFasmWriter
write_enum(cell, "LF_OUTPUT_EN");
write_enum(cell, "DTR_EN", "ENABLED");
write_enum(cell, "DEBUG_N", "DISABLED");
- write_int_vector(stringf("HF_CLK_DIV[7:0]"), ctx->parse_lattice_param_from_cell(cell, id_HF_CLK_DIV, 8, 0).intval, 8);
+ write_int_vector(stringf("HF_CLK_DIV[7:0]"),
+ ctx->parse_lattice_param_from_cell(cell, id_HF_CLK_DIV, 8, 0).intval, 8);
write_int_vector(stringf("HF_SED_SEC_DIV[7:0]"), 1, 8);
write_cell_muxes(cell);
pop(2);
@@ -812,9 +813,10 @@ struct NexusFasmWriter
};
/* clang-format on */
- static bool is_number(std::string s) {
- for (auto c : s) {
- if(!isdigit(c))
+ static bool is_number(std::string s)
+ {
+ for (auto c : s) {
+ if (!isdigit(c))
return false;
}
return true;
@@ -844,12 +846,11 @@ struct NexusFasmWriter
if (fnd_word != pll_word_params.end()) {
if (cell->params.count(n)) {
write_int_vector(stringf("%s[%d:0]", name.c_str(), fnd_word->second - 1),
- ctx->parse_lattice_param_from_cell(cell, n, fnd_word->second, 0).as_int64(),
- fnd_word->second);
+ ctx->parse_lattice_param_from_cell(cell, n, fnd_word->second, 0).as_int64(),
+ fnd_word->second);
} else {
write_int_vector(stringf("%s[%d:0]", name.c_str(), fnd_word->second - 1),
- ctx->parse_lattice_param(temp, n, fnd_word->second).as_int64(),
- fnd_word->second);
+ ctx->parse_lattice_param(temp, n, fnd_word->second).as_int64(), fnd_word->second);
}
} else {
if (cell->params.count(n)) {
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 4eccc634..0870bf40 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -41,7 +41,7 @@ Property Arch::parse_lattice_param_from_cell(const CellInfo *ci, IdString prop,
}
// Parse a possibly-Lattice-style (C literal in Verilog string) style parameter
-Property Arch::parse_lattice_param(const Property &val, IdString prop, int width, const char* ci) const
+Property Arch::parse_lattice_param(const Property &val, IdString prop, int width, const char *ci) const
{
if (val.is_string) {
const std::string &s = val.str;
@@ -84,8 +84,7 @@ Property Arch::parse_lattice_param(const Property &val, IdString prop, int width
for (auto b : temp.str.substr(width)) {
if (b == Property::S1)
- log_error("Found value for property %s.%s with width greater than %d\n", ci, nameOf(prop),
- width);
+ log_error("Found value for property %s.%s with width greater than %d\n", ci, nameOf(prop), width);
}
temp.update_intval();
return temp.extract(0, width);