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* ice40: Fix BRAM NegClk bitstream logicgatecat2023-03-201-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cmake: Make HeAP placer always-enabledgatecat2023-03-171-10/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Add python binding for write_bitstreamgatecat2023-02-281-0/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1090 from rowanG077/ecp5-propagate-dcsc-clk-ctmyrtle2023-02-131-2/+4
|\ | | | | ecp5: Propagate clock constraints through DCSC
| * streamline constant_net detectionrowanG0772023-02-061-2/+4
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* | ice40: Don't assert on unknown extra_config bits if they are 0Sylvain Munaut2023-02-011-1/+5
| | | | | | | | | | | | | | Bits are 0 by default anyway, so if they are unknown (because icestorm is too od) but we want them at 0 ... it's not much of an issue. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Add support for PLL ICEGATE functionSylvain Munaut2023-02-013-13/+19
|/ | | | | | | | | Technically you can enable it independently on CORE and GLOBAL output, but this is not exposed in the classic primitive, so we do the same as icecube2 and enable/disable it for both output path depending on the argument Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Support for undriven / unconnected output portsSylvain Munaut2023-01-291-1/+6
| | | | | | | | If a port specified as output (and thus had a $nextpnr_obuf inserted) is undriven (const `z` or const `x`), we make sure to not enable the output driver. Also enable pull-ups if it was requested by the user. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Rework pull-up attribute copy to SB_IO blocksSylvain Munaut2023-01-291-8/+14
| | | | | | | | | | | | | | | We try to copy the attribute only when there is a chance for the output driver to not be active. Note that this can _also_ happen when a port is specified as output but has a TBUF, which the previous code wasn't handling. We could copy the attribute "all-the-time" but this would mean if a user specified a `-pullup yes` in the PCF for a permanently driven output pin, we'd be burning power for nothing. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add debugs to isBelLocationValid for SB_IOSean Anderson2022-12-071-4/+22
| | | | | | | | | | | | | | | | | When there is a constraint conflict while placing IOs, the user gets an error message such as ERROR: Bel 'X0/Y27/io1' of type 'SB_IO' is not valid for cell 'my_pin' of type 'SB_IO' While this identifies the problematic cell, it does not explain why there is a problem. Add some verbose messages to allow users to determine where the problem is. This can result in something like Info: Net '$PACKER_VCC_NET' for cell 'my_pin' conflicts with net 'ce' for 'ce_pin' which provides something actionable. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* api: add explain_invalid option to isBelLocationValidgatecat2022-12-072-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-072-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-021-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Correct Not Equal operator implementation in ice40Tyler2022-10-171-1/+1
| | | I noticed this during my work reimplementing nextpnr, and it seems to be dead and wrong, or at least dead. Either way I think this is what was intended unless anyone can correct me.
* ice40: Fix handling of carry out route-thru via 25,14gatecat2022-09-261-15/+21
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: implement checkPipAvailForNetgatecat2022-09-201-0/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Fix UltraPlus BRAM clock polaritygatecat2022-09-141-3/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use CMake's Python3 rather than PythonInterp in subdirsAdam Sampson2022-08-211-2/+2
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* refactor: Use IdString::in instead of || chainsgatecat2022-08-106-42/+35
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Fix accidental creation of empty portsgatecat2022-06-251-9/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Fix propagation of constraints through SB_GBgatecat2022-05-081-7/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Avoid chain finder from mixing up chains by only allowing I3 chaining ↵gatecat2022-04-111-34/+45
| | | | | | at end Signed-off-by: gatecat <gatecat@ds0.me>
* ci: Restructure and move entirely to GH actions from Cirrusgatecat2022-04-081-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Fix wirenames containing / which is the list separatorgatecat2022-03-301-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Merge driving LUT<=2s into carry-only LCsgatecat2022-03-293-3/+90
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Improve error reporting for PLL conflictsgatecat2022-03-251-7/+32
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2022-03-171-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: fix crash when packing LUTs with no outputStefan Riesenberger2022-03-141-24/+27
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* Switch to potentially-sparse net users arraygatecat2022-02-274-92/+54
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-183-47/+50
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-1610-660/+798
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use cell member functions to add portsgatecat2022-02-161-169/+162
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-164-52/+26
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* Merge pull request #873 from YosysHQ/gatecat/ice40-carry-lutgatecat2022-01-161-0/+2
|\ | | | | ice40: Pack LUT at start of carry chain if there is 1 candidate
| * ice40: Pack LUT at start of carry chain if there is 1 candidategatecat2021-12-141-0/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-6/+6
|/ | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Use default value when IP is missing BUS_ADDR74 parametergatecat2021-07-201-3/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Fix order of values in errorgatecat2021-07-101-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-1226-44/+44
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove redundant code after hashlib movegatecat2021-06-021-46/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-026-22/+21
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib in routersgatecat2021-06-021-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-024-39/+42
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add hash() member functionsgatecat2021-06-021-0/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add default base implementation of cluster APIgatecat2021-05-062-2/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-152-8/+20
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-194-72/+42
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-163-123/+94
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>