aboutsummaryrefslogtreecommitdiffstats
path: root/ice40
diff options
context:
space:
mode:
authorgatecat <gatecat@ds0.me>2021-12-19 16:41:34 +0000
committergatecat <gatecat@ds0.me>2021-12-19 17:15:15 +0000
commitddb084e9a8a0cba10536951236cde824526e8071 (patch)
treed03ba5688367cb476a06b19d04ca78d0352afce3 /ice40
parent56d550733346000584b9490fac0953fe07124035 (diff)
downloadnextpnr-ddb084e9a8a0cba10536951236cde824526e8071.tar.gz
nextpnr-ddb084e9a8a0cba10536951236cde824526e8071.tar.bz2
nextpnr-ddb084e9a8a0cba10536951236cde824526e8071.zip
archapi: Use arbitrary rather than actual placement in predictDelay
This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'ice40')
-rw-r--r--ice40/arch.h2
-rw-r--r--ice40/delay.cc10
2 files changed, 6 insertions, 6 deletions
diff --git a/ice40/arch.h b/ice40/arch.h
index 5162285c..3563baad 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -784,7 +784,7 @@ struct Arch : BaseArch<ArchRanges>
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const override;
- delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+ delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
delay_t getDelayEpsilon() const override { return 20; }
delay_t getRipupDelayPenalty() const override { return 200; }
float getDelayNS(delay_t v) const override { return v * 0.001; }
diff --git a/ice40/delay.cc b/ice40/delay.cc
index 740057f1..a00cc259 100644
--- a/ice40/delay.cc
+++ b/ice40/delay.cc
@@ -188,13 +188,13 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
return v;
}
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
{
- const auto &driver = net_info->driver;
- auto driver_loc = getBelLocation(driver.cell->bel);
- auto sink_loc = getBelLocation(sink.cell->bel);
+ NPNR_UNUSED(dst_pin);
+ auto driver_loc = getBelLocation(src_bel);
+ auto sink_loc = getBelLocation(dst_bel);
- if (driver.port == id_COUT) {
+ if (src_pin == id_COUT) {
if (driver_loc.y == sink_loc.y)
return 0;
return 250;