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* synth: add a flag to force creation of variablesTristan Gingold2022-05-115-9/+21
* ghdlsynth.adb: remove -E experimental commandTristan Gingold2022-05-101-145/+42
* synth: add current_stmt, minor reworkTristan Gingold2022-05-094-61/+99
* synth-vhdl_insts: handle interfaces of type interface type. Fix #2053Tristan Gingold2022-05-071-1/+12
* vhdl: consider fully static record aggregates. Fix #2051Tristan Gingold2022-05-074-26/+83
* ortho/debug: handle aggregates of record-subtypeTristan Gingold2022-05-073-7/+25
* elab-vhdl_context: introduce signal_indexTristan Gingold2022-05-063-3/+12
* vhdl-sem.adb(are_trees_equal): handle selected element. Fix #2050Tristan Gingold2022-05-061-0/+4
* vhdl-sem_names: second fix for #2048Tristan Gingold2022-05-031-1/+2
* synth-vhdl_context: resize table before access. Fix #2049Tristan Gingold2022-05-021-6/+14
* vhdl-sem_names(sem_selected_by_all_name): avoid a crashTristan Gingold2022-05-021-0/+4
* vhdl-sem_assocs: avoid a crash after forced analysisTristan Gingold2022-05-021-0/+5
* netlists: fix incorrect access (realloc). Fix #2046Tristan Gingold2022-05-021-8/+11
* elab-vhdl_debug: also print objects in disp_hierarchyTristan Gingold2022-05-013-59/+140
* elab-vhdl_objtypes: fix restart of libghdlTristan Gingold2022-04-303-7/+25
* synth: avoid a crash after an errorTristan Gingold2022-04-292-0/+19
* elab-vhdl_insts: use block configuration from configurationTristan Gingold2022-04-291-3/+6
* synth: adjust elab-debugger__on.adbTristan Gingold2022-04-291-8/+4
* ghdlsynth: add experimental command -ETristan Gingold2022-04-291-8/+133
* elab-vhdl_types: do not crash on signal resolverTristan Gingold2022-04-291-0/+3
* synth-vhdl_eval: handle all comparisons for enumsTristan Gingold2022-04-291-33/+29
* synth-vhdl_decls: handle attributes on input portsTristan Gingold2022-04-291-2/+10
* vhdl-annotations: do not annotate type for signal attributesTristan Gingold2022-04-291-2/+0
* options: add -fpragma-translate options (for debug purposes)Tristan Gingold2022-04-291-0/+3
* ghdldrv: allow --work within files for import commandTristan Gingold2022-04-291-19/+60
* synth: extract elab-vhdl_debug from elab-debuggerTristan Gingold2022-04-293-465/+662
* vhdl-nodes: reorder, add iir_kinds_structural_statementTristan Gingold2022-04-291-9/+17
* elab-vhdl_insts: handle open unconstrained port associationTristan Gingold2022-04-291-0/+3
* synth-vhdl_stmts: handle static evaluation for cond variable assignmentTristan Gingold2022-04-281-18/+53
* ghdllib: adjust first line comment (pasto)Tristan Gingold2022-04-282-2/+2
* netlists-memories: detect simple loop. Fix #2043Tristan Gingold2022-04-281-3/+10
* synth-ieee-numeric_std: factorize codeTristan Gingold2022-04-281-14/+5
* synth-vhdl_eval: handle absTristan Gingold2022-04-273-19/+61
* synth-vhdl_stmts: add implicit conversion for cond assignmentTristan Gingold2022-04-271-0/+5
* synth: renaming (synth-static_oper -> synth-vhdl_eval)Tristan Gingold2022-04-274-62/+61
* synth-static_oper: abstract codeTristan Gingold2022-04-271-21/+30
* vhdl-sem_expr: minor renamingTristan Gingold2022-04-271-3/+6
* vhdl-sem_expr: add a commentTristan Gingold2022-04-271-0/+21
* synth-static_oper: handle bit/boolean array element operationsTristan Gingold2022-04-272-3/+29
* vhdl: handle static expressions with ieee operationsTristan Gingold2022-04-262-12/+370
* ghdldrv: call elab.vhdl_objtypes.init in optionsTristan Gingold2022-04-262-3/+3
* synth: abstract code for reuse by evaluationTristan Gingold2022-04-267-52/+78
* synth-static_oper: fully remove dependency on synth_instanceTristan Gingold2022-04-263-39/+44
* synth-static_oper: do not depend on instance for static operations.Tristan Gingold2022-04-267-62/+91
* vhdl: avoid a crash after errors in associations for packagesTristan Gingold2022-04-223-96/+115
* netlists-disp_verilog: output default value for pmux. Fix #2041Tristan Gingold2022-04-211-0/+1
* vhdl-sem_names.adb: avoid a crash on incorrect type markTristan Gingold2022-04-202-1/+12
* ghdldrv: add --all option to dir commandYuni Tsukiyama2022-04-191-3/+61
* trans-chap2.adb: adjust owner_subtype for instantiations. Fix #2026Tristan Gingold2022-04-152-0/+39
* vhdl-sem_names(sem_check_all_sensitized): only consider interface signalTristan Gingold2022-04-152-3/+14
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