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authorTristan Gingold <tgingold@free.fr>2022-05-11 05:21:40 +0200
committerTristan Gingold <tgingold@free.fr>2022-05-11 05:21:40 +0200
commitfe2afd6a3dd1a9a1234ca095fd63d0e8c999a4d7 (patch)
treea6138c037a8c16f8dae637ff94b2dd9400377ce8 /src
parent0a81d6f1ec4106a8e8c90fe455269382e87cc48d (diff)
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synth: add a flag to force creation of variables
Diffstat (limited to 'src')
-rw-r--r--src/synth/elab-vhdl_decls.adb18
-rw-r--r--src/synth/elab-vhdl_decls.ads5
-rw-r--r--src/synth/elab-vhdl_insts.adb2
-rw-r--r--src/synth/synth-vhdl_stmts.adb3
-rw-r--r--src/synth/synth-vhdl_stmts.ads2
5 files changed, 21 insertions, 9 deletions
diff --git a/src/synth/elab-vhdl_decls.adb b/src/synth/elab-vhdl_decls.adb
index 897705e37..87c5dbd50 100644
--- a/src/synth/elab-vhdl_decls.adb
+++ b/src/synth/elab-vhdl_decls.adb
@@ -120,7 +120,8 @@ package body Elab.Vhdl_Decls is
end Elab_Signal_Declaration;
procedure Elab_Variable_Declaration (Syn_Inst : Synth_Instance_Acc;
- Decl : Node)
+ Decl : Node;
+ Force_Init : Boolean)
is
Def : constant Node := Get_Default_Value (Decl);
Decl_Type : constant Node := Get_Type (Decl);
@@ -138,7 +139,11 @@ package body Elab.Vhdl_Decls is
Init := Exec_Expression_With_Type (Syn_Inst, Def, Obj_Typ);
Init := Exec_Subtype_Conversion (Init, Obj_Typ, False, Decl);
else
- Init := (Typ => Obj_Typ, Val => null);
+ if Force_Init then
+ Init := Create_Value_Default (Obj_Typ);
+ else
+ Init := (Typ => Obj_Typ, Val => null);
+ end if;
end if;
Create_Object (Syn_Inst, Decl, Init);
end Elab_Variable_Declaration;
@@ -220,11 +225,12 @@ package body Elab.Vhdl_Decls is
procedure Elab_Declaration (Syn_Inst : Synth_Instance_Acc;
Decl : Node;
+ Force_Init : Boolean;
Last_Type : in out Node) is
begin
case Get_Kind (Decl) is
when Iir_Kind_Variable_Declaration =>
- Elab_Variable_Declaration (Syn_Inst, Decl);
+ Elab_Variable_Declaration (Syn_Inst, Decl, Force_Init);
-- when Iir_Kind_Interface_Variable_Declaration =>
-- -- Ignore default value.
-- Create_Wire_Object (Syn_Inst, Wire_Variable, Decl);
@@ -280,7 +286,9 @@ package body Elab.Vhdl_Decls is
end case;
end Elab_Declaration;
- procedure Elab_Declarations (Syn_Inst : Synth_Instance_Acc; Decls : Iir)
+ procedure Elab_Declarations (Syn_Inst : Synth_Instance_Acc;
+ Decls : Iir;
+ Force_Init : Boolean := False)
is
Decl : Node;
Last_Type : Node;
@@ -288,7 +296,7 @@ package body Elab.Vhdl_Decls is
Last_Type := Null_Node;
Decl := Decls;
while Is_Valid (Decl) loop
- Elab_Declaration (Syn_Inst, Decl, Last_Type);
+ Elab_Declaration (Syn_Inst, Decl, Force_Init, Last_Type);
exit when Is_Error (Syn_Inst);
diff --git a/src/synth/elab-vhdl_decls.ads b/src/synth/elab-vhdl_decls.ads
index 5937e1f58..8e45897b1 100644
--- a/src/synth/elab-vhdl_decls.ads
+++ b/src/synth/elab-vhdl_decls.ads
@@ -26,9 +26,12 @@ package Elab.Vhdl_Decls is
procedure Elab_Declaration (Syn_Inst : Synth_Instance_Acc;
Decl : Node;
+ Force_Init : Boolean;
Last_Type : in out Node);
- procedure Elab_Declarations (Syn_Inst : Synth_Instance_Acc; Decls : Iir);
+ procedure Elab_Declarations (Syn_Inst : Synth_Instance_Acc;
+ Decls : Iir;
+ Force_Init : Boolean := False);
procedure Finalize_Declaration (Syn_Inst : Synth_Instance_Acc;
Decl : Iir;
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb
index d02691de0..820e20ff1 100644
--- a/src/synth/elab-vhdl_insts.adb
+++ b/src/synth/elab-vhdl_insts.adb
@@ -418,7 +418,7 @@ package body Elab.Vhdl_Insts is
| Iir_Kind_Subtype_Declaration
| Iir_Kind_Type_Declaration
| Iir_Kind_Anonymous_Type_Declaration =>
- Elab_Declaration (Unit_Inst, Item, Last_Type);
+ Elab_Declaration (Unit_Inst, Item, False, Last_Type);
when Iir_Kinds_Concurrent_Signal_Assignment
| Iir_Kinds_Process_Statement
| Iir_Kinds_Generate_Statement
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index 3c52138e5..906668027 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -2357,8 +2357,7 @@ package body Synth.Vhdl_Stmts is
Areapools.Release (Area_Mark, Instance_Pool.all);
end Synth_Implicit_Procedure_Call;
- procedure Synth_Procedure_Call
- (Syn_Inst : Synth_Instance_Acc; Stmt : Node)
+ procedure Synth_Procedure_Call (Syn_Inst : Synth_Instance_Acc; Stmt : Node)
is
Call : constant Node := Get_Procedure_Call (Stmt);
Imp : constant Node := Get_Implementation (Call);
diff --git a/src/synth/synth-vhdl_stmts.ads b/src/synth/synth-vhdl_stmts.ads
index d07abb9aa..b590b8ead 100644
--- a/src/synth/synth-vhdl_stmts.ads
+++ b/src/synth/synth-vhdl_stmts.ads
@@ -105,6 +105,8 @@ package Synth.Vhdl_Stmts is
procedure Synth_Variable_Assignment (Inst : Synth_Instance_Acc;
Stmt : Node);
+ procedure Synth_Procedure_Call (Syn_Inst : Synth_Instance_Acc; Stmt : Node);
+
-- Return the statements chain to be executed.
function Execute_Static_Case_Statement
(Inst : Synth_Instance_Acc; Stmt : Node; Sel : Valtyp) return Node;