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| author | Tristan Gingold <tgingold@free.fr> | 2022-04-29 08:47:16 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-04-29 08:47:16 +0200 |
| commit | f9a32a4e94080760da1a6d584604c4df08c9ee51 (patch) | |
| tree | 7ece1b1034f556aef83df7f048340f183e33fcb2 /src | |
| parent | 5013d867c156c35d28ecaffd840e80e25d64c119 (diff) | |
| download | ghdl-f9a32a4e94080760da1a6d584604c4df08c9ee51.tar.gz ghdl-f9a32a4e94080760da1a6d584604c4df08c9ee51.tar.bz2 ghdl-f9a32a4e94080760da1a6d584604c4df08c9ee51.zip | |
vhdl-nodes: reorder, add iir_kinds_structural_statement
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index cc9279d1b..1e97286d0 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -6594,10 +6594,6 @@ package Vhdl.Nodes is Iir_Kind_Function_Body .. Iir_Kind_Procedure_Body; - subtype Iir_Kinds_Process_Statement is Iir_Kind range - Iir_Kind_Sensitized_Process_Statement .. - Iir_Kind_Process_Statement; - subtype Iir_Kinds_Interface_Object_Declaration is Iir_Kind range Iir_Kind_Interface_Constant_Declaration .. --Iir_Kind_Interface_Variable_Declaration @@ -6891,6 +6887,14 @@ package Vhdl.Nodes is --Iir_Kind_For_Generate_Statement Iir_Kind_Component_Instantiation_Statement; + -- Nice classification from AMS vhdl. + subtype Iir_Kinds_Structural_Statement is Iir_Kind range + Iir_Kind_Block_Statement .. + --Iir_Kind_If_Generate_Statement + --Iir_Kind_Case_Generate_Statement + --Iir_Kind_For_Generate_Statement + Iir_Kind_Component_Instantiation_Statement; + subtype Iir_Kinds_Simple_Concurrent_Statement is Iir_Kind range Iir_Kind_Sensitized_Process_Statement .. --Iir_Kind_Process_Statement @@ -6905,6 +6909,15 @@ package Vhdl.Nodes is --Iir_Kind_Psl_Cover_Directive Iir_Kind_Psl_Restrict_Directive; + subtype Iir_Kinds_Process_Statement is Iir_Kind range + Iir_Kind_Sensitized_Process_Statement .. + Iir_Kind_Process_Statement; + + subtype Iir_Kinds_Concurrent_Signal_Assignment is Iir_Kind range + Iir_Kind_Concurrent_Simple_Signal_Assignment .. + --Iir_Kind_Concurrent_Conditional_Signal_Assignment + Iir_Kind_Concurrent_Selected_Signal_Assignment; + subtype Iir_Kinds_Psl_Property_Directive is Iir_Kind range Iir_Kind_Psl_Assert_Directive .. Iir_Kind_Psl_Assume_Directive; @@ -6924,11 +6937,6 @@ package Vhdl.Nodes is --Iir_Kind_Case_Generate_Statement Iir_Kind_For_Generate_Statement; - subtype Iir_Kinds_Concurrent_Signal_Assignment is Iir_Kind range - Iir_Kind_Concurrent_Simple_Signal_Assignment .. - --Iir_Kind_Concurrent_Conditional_Signal_Assignment - Iir_Kind_Concurrent_Selected_Signal_Assignment; - subtype Iir_Kinds_If_Case_Generate_Statement is Iir_Kind range Iir_Kind_If_Generate_Statement .. Iir_Kind_Case_Generate_Statement; |