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| author | Tristan Gingold <tgingold@free.fr> | 2022-04-29 12:01:06 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-04-29 12:01:06 +0200 |
| commit | b11fee56745c0cf2121831eec160023aceabf2e4 (patch) | |
| tree | e281e4ab41dac3ab661c4c491ac11f1e8cddb597 /src | |
| parent | b2737f9e48bc941c73b431b4e267299708fc1ad5 (diff) | |
| download | ghdl-b11fee56745c0cf2121831eec160023aceabf2e4.tar.gz ghdl-b11fee56745c0cf2121831eec160023aceabf2e4.tar.bz2 ghdl-b11fee56745c0cf2121831eec160023aceabf2e4.zip | |
synth-vhdl_decls: handle attributes on input ports
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_decls.adb | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb index 8d38eaaff..840663054 100644 --- a/src/synth/synth-vhdl_decls.adb +++ b/src/synth/synth-vhdl_decls.adb @@ -206,6 +206,7 @@ package body Synth.Vhdl_Decls is is Obj : constant Node := Get_Designated_Entity (Attr_Value); Id : constant Name_Id := Get_Identifier (Attr_Decl); + N : Net; Inst : Instance; V : Valtyp; Ptype : Param_Type; @@ -221,8 +222,15 @@ package body Synth.Vhdl_Decls is | Iir_Kind_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration => V := Get_Value (Syn_Inst, Obj); - pragma Assert (V.Val.Kind = Value_Wire); - Inst := Get_Net_Parent (Get_Wire_Gate (Get_Value_Wire (V.Val))); + case V.Val.Kind is + when Value_Wire => + N := Get_Wire_Gate (Get_Value_Wire (V.Val)); + when Value_Net => + N := Get_Value_Net (V.Val); + when others => + raise Internal_Error; + end case; + Inst := Get_Net_Parent (N); when Iir_Kind_Component_Instantiation_Statement => -- TODO return; |