iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl: handle cover and restrict within vunit.	Tristan Gingold	2019-10-15	5	-1/+17
*	synth: handle overflow literal.	Tristan Gingold	2019-10-15	2	-1/+9
*	netlists: declare memory gates.	Tristan Gingold	2019-10-15	3	-3/+215
*	synth-expr: handle any discrete_range in aggregate choices.	Tristan Gingold	2019-10-15	1	-1/+2
*	synth-insts: accept architecture instantiation in synth_dependencies.	Tristan Gingold	2019-10-15	1	-2/+3
*	Use Decode_Work_Option in options. Factorize code.	Tristan Gingold	2019-10-15	4	-25/+11
*	ghdlsynth: allow --work= option in the middle of files.	Tristan Gingold	2019-10-15	3	-1/+48
*	synth-inference: handle multiple connections.	Tristan Gingold	2019-10-14	1	-14/+31
*	synth-infere: extract clock from and tree.	Tristan Gingold	2019-10-14	1	-17/+102
*	netlists-dump: do not print name of anonymous parameters.	Tristan Gingold	2019-10-14	1	-2/+6
*	synth-infere: fix partial assignment with clock enable.	Tristan Gingold	2019-10-14	1	-2/+9
*	vhdl-evaluation: handle bit condition operator. Fix #977	Tristan Gingold	2019-10-13	1	-0/+3
*	synth: handle constants for condition operator.	Tristan Gingold	2019-10-13	3	-1/+20
*	synth-stmts: fix thinko (need to adjust type for indexed a 1-bit array).	Tristan Gingold	2019-10-13	1	-2/+5
*	synth-stmts: handle const indexed array.	Tristan Gingold	2019-10-13	1	-0/+5
*	synth-oper: handle const array array concat.	Tristan Gingold	2019-10-13	1	-16/+41
*	synth-oper: add more operations (float div, less for arrays)	Tristan Gingold	2019-10-13	1	-7/+39
*	synth-stmts: improve support for associations in function calls.	Tristan Gingold	2019-10-13	1	-19/+92
*	synth-inst: minor refactoring.	Tristan Gingold	2019-10-13	1	-3/+2
*	synth-oper: handle unsigned unsigned mul.	Tristan Gingold	2019-10-13	1	-0/+13
*	synth-expr: handle integer type conversion.	Tristan Gingold	2019-10-13	1	-1/+4
*	synth-expr: handle range array attribute in slices.	Tristan Gingold	2019-10-13	1	-42/+74
*	vhdl-annotations: handle list of record elements declaration.	Tristan Gingold	2019-10-13	1	-2/+4
*	vhdl: recognize std_logic_unsigned.conv_integer.	Tristan Gingold	2019-10-13	3	-2/+12
*	netlists-iterators: avoid a crash if no ports.	Tristan Gingold	2019-10-13	1	-3/+1
*	netlists-dump: improve output.	Tristan Gingold	2019-10-13	1	-9/+28
*	netlists-builders: adjust names of dyn_extract ports.	Tristan Gingold	2019-10-13	1	-2/+2
*	Show error on wait without condition (#976)	Pepijn de Vos	2019-10-13	1	-0/+4
*	add record (in)equality (#975)	Pepijn de Vos	2019-10-13	1	-2/+4
*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	5	-23/+40
*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	7	-18/+69
*	vhdl: recognize minus from std_logic_unsigned	Tristan Gingold	2019-10-11	3	-1/+17
*	vhdl: do not try to recognize mentor version of std_logic_arith.	Tristan Gingold	2019-10-10	1	-0/+7
*	synth: remove synth-types	Tristan Gingold	2019-10-10	4	-91/+13
*	netlists: add internings child package.	Tristan Gingold	2019-10-10	3	-14/+61
*	ghdlsynth: add --out=none to not display the result.	Tristan Gingold	2019-10-10	1	-1/+6
*	netlists-disp_vhdl: fix pasto on id_asr.	Tristan Gingold	2019-10-10	1	-5/+5
*	vhdl: improve error message for redefinition of library	Tristan Gingold	2019-10-10	1	-1/+1
*	synth: handle constants for enum equality.	Tristan Gingold	2019-10-10	1	-1/+5
*	netlists: give a name to the free module.	Tristan Gingold	2019-10-10	1	-2/+4
*	synth: rewrite cleanup pass.	Tristan Gingold	2019-10-10	7	-68/+188
*	synth-decls: ignore use clauses.	Tristan Gingold	2019-10-10	1	-0/+2
*	synth-opeer: extend synth_uresize	Tristan Gingold	2019-10-10	1	-1/+1
*	synth-oper: handle more operators.	Tristan Gingold	2019-10-10	1	-3/+6
*	vhdl: recognize conv_unsigned from ieee.std_logic_arith.	Tristan Gingold	2019-10-10	6	-4/+206
*	synth: set name on generate statements.	Tristan Gingold	2019-10-09	2	-6/+16
*	synth: set location on instances.	Tristan Gingold	2019-10-09	1	-0/+1
*	synth: use synth.source for setting location.	Tristan Gingold	2019-10-09	8	-17/+34
*	netlists-disp_vhdl: handle const_SB32	Tristan Gingold	2019-10-09	1	-1/+2
*	synth-environment: fix a thinko.	Tristan Gingold	2019-10-09	1	-1/+2