vhdl: handle cover and restrict within vunit.

5 files changed, 17 insertions, 1 deletions

diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index 7ebeb1a5b..292934645 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -2591,6 +2591,8 @@ package body Synth.Stmts is
                Synth_Psl_Assert_Directive (Syn_Inst, Item);
             when Iir_Kind_Psl_Assume_Directive =>
                Synth_Psl_Assume_Directive (Syn_Inst, Item);
+            when Iir_Kind_Psl_Restrict_Directive =>
+               Synth_Psl_Restrict_Directive (Syn_Inst, Item);
             when Iir_Kind_Psl_Cover_Directive =>
                Synth_Psl_Cover_Directive (Syn_Inst, Item);
             when others =>
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb
index fb24402c8..660a5001d 100644
--- a/src/vhdl/vhdl-annotations.adb
+++ b/src/vhdl/vhdl-annotations.adb
@@ -1181,7 +1181,9 @@ package body Vhdl.Annotations is
             when Iir_Kind_Psl_Default_Clock =>
                null;
             when Iir_Kind_Psl_Assert_Directive
-              | Iir_Kind_Psl_Assume_Directive =>
+               | Iir_Kind_Psl_Assume_Directive
+               | Iir_Kind_Psl_Cover_Directive
+               | Iir_Kind_Psl_Restrict_Directive =>
                null;
             when others =>
                Error_Kind ("annotate_vunit_declaration", Item);
diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb
index 1a4b99d40..bddcc228f 100644
--- a/src/vhdl/vhdl-canon.adb
+++ b/src/vhdl/vhdl-canon.adb
@@ -3241,6 +3241,10 @@ package body Vhdl.Canon is
                Canon_Psl_Assert_Directive (Item);
             when Iir_Kind_Psl_Assume_Directive =>
                Canon_Psl_Property_Directive (Item);
+            when Iir_Kind_Psl_Restrict_Directive =>
+               Canon_Psl_Sequence_Directive (Item);
+            when Iir_Kind_Psl_Cover_Directive =>
+               Canon_Psl_Cover_Directive (Item);
             when others =>
                Error_Kind ("canon_psl_verification_unit", Item);
          end case;
diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb
index 094889e28..1b498fbf1 100644
--- a/src/vhdl/vhdl-parse.adb
+++ b/src/vhdl/vhdl-parse.adb
@@ -9836,6 +9836,10 @@ package body Vhdl.Parse is
                Item := Parse_Psl_Assume_Directive (True);
             when Tok_Assert =>
                Item := Parse_Psl_Assert_Directive (True);
+            when Tok_Restrict =>
+               Item := Parse_Psl_Restrict_Directive (True);
+            when Tok_Cover =>
+               Item := Parse_Psl_Cover_Directive (True);
             when others =>
                exit;
          end case;
diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb
index e4823cd69..bd8f98b13 100644
--- a/src/vhdl/vhdl-sem_psl.adb
+++ b/src/vhdl/vhdl-sem_psl.adb
@@ -980,6 +980,10 @@ package body Vhdl.Sem_Psl is
                Item := Sem_Psl_Assert_Directive (Item, False);
             when Iir_Kind_Psl_Assume_Directive =>
                Sem_Psl_Assume_Directive (Item);
+            when Iir_Kind_Psl_Restrict_Directive =>
+               Sem_Psl_Restrict_Directive (Item);
+            when Iir_Kind_Psl_Cover_Directive =>
+               Sem_Psl_Cover_Directive (Item);
             when others =>
                Error_Kind ("sem_psl_verification_unit", Item);
          end case;