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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-10 18:40:17 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-10 18:40:17 +0200 |
| commit | 1ee18afbe800ede060e8e0daca47b188137ee4eb (patch) | |
| tree | 4458c6efe361472d3f9779f8b11c742ab1ac6673 /src | |
| parent | 8312977d2ff9eda57c43fe0d028fe261a063fe24 (diff) | |
| download | ghdl-1ee18afbe800ede060e8e0daca47b188137ee4eb.tar.gz ghdl-1ee18afbe800ede060e8e0daca47b188137ee4eb.tar.bz2 ghdl-1ee18afbe800ede060e8e0daca47b188137ee4eb.zip | |
netlists-disp_vhdl: fix pasto on id_asr.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 05e94c205..880bfb0db 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -770,10 +770,14 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= std_logic_vector " & "(shift_left (\ui0, to_integer (\ui1)));" & NL, Inst); + when Id_Lsr => + Disp_Template + (" \o0 <= std_logic_vector " + & "(shift_right (\ui0, to_integer(\ui1)));" & NL, Inst); when Id_Asr => Disp_Template (" \o0 <= std_logic_vector " - & "(shift_left (\si0, to_integer (\ui1)));" & NL, Inst); + & "(shift_right (\si0, to_integer (\ui1)));" & NL, Inst); when Id_Rol => Disp_Template (" \o0 <= std_logic_vector " @@ -881,10 +885,6 @@ package body Netlists.Disp_Vhdl is Inst, (0 => Ow)); end if; end; - when Id_Lsr => - Disp_Template - (" \o0 <= std_logic_vector " - & "(shift_right (\ui0, to_integer(\ui1)));" & NL, Inst); when Id_Red_Or => declare Iw : constant Width := Get_Width (Get_Input_Net (Inst, 0)); |