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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-12 07:07:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-13 18:54:22 +0200 |
| commit | b513a6170db4fe14eb6e885e859445d763633266 (patch) | |
| tree | 5c9339dd6eb0183c678beacb12ebd00c9abd3414 /src | |
| parent | f7300b2906b6c918c83b6037d7223e7409dd440e (diff) | |
| download | ghdl-b513a6170db4fe14eb6e885e859445d763633266.tar.gz ghdl-b513a6170db4fe14eb6e885e859445d763633266.tar.bz2 ghdl-b513a6170db4fe14eb6e885e859445d763633266.zip | |
vhdl: recognize std_logic_unsigned.conv_integer.
Handle more operators in synth.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-oper.adb | 7 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 5 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 2 |
3 files changed, 12 insertions, 2 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index d6574667b..8f85a8817 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -513,7 +513,9 @@ package body Synth.Oper is | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => -- "-" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Id_Sub); - when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns => + when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl => -- "-" (Unsigned, Unsigned) return Synth_Dyadic_Uns (Id_Sub, True); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int @@ -1078,7 +1080,8 @@ package body Synth.Oper is end if; end; when Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer => -- UNSIGNED to Natural. declare Int_Type : constant Type_Acc := diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 9e2bb5269..c3b30be8e 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -184,6 +184,11 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is else -- Monadic function. case Get_Identifier (Decl) is + when Name_Conv_Integer => + if Sign = Pkg_Unsigned then + Res := + Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer; + end if; when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index bd25fb805..8de95478b 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5093,6 +5093,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer, + -- Std_Logic_Signed (synopsys extension). Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, |