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* vhdl: Add the implicit [*] at start of PSL cover sequence.Tristan Gingold2019-10-153-0/+37
* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-155-1/+17
* synth: handle overflow literal.Tristan Gingold2019-10-152-1/+9
* netlists: declare memory gates.Tristan Gingold2019-10-153-3/+215
* synth-expr: handle any discrete_range in aggregate choices.Tristan Gingold2019-10-151-1/+2
* synth-insts: accept architecture instantiation in synth_dependencies.Tristan Gingold2019-10-151-2/+3
* Use Decode_Work_Option in options. Factorize code.Tristan Gingold2019-10-154-25/+11
* ghdlsynth: allow --work= option in the middle of files.Tristan Gingold2019-10-153-1/+48
* synth-inference: handle multiple connections.Tristan Gingold2019-10-141-14/+31
* synth-infere: extract clock from and tree.Tristan Gingold2019-10-141-17/+102
* netlists-dump: do not print name of anonymous parameters.Tristan Gingold2019-10-141-2/+6
* synth-infere: fix partial assignment with clock enable.Tristan Gingold2019-10-141-2/+9
* vhdl-evaluation: handle bit condition operator. Fix #977Tristan Gingold2019-10-131-0/+3
* synth: handle constants for condition operator.Tristan Gingold2019-10-133-1/+20
* synth-stmts: fix thinko (need to adjust type for indexed a 1-bit array).Tristan Gingold2019-10-131-2/+5
* synth-stmts: handle const indexed array.Tristan Gingold2019-10-131-0/+5
* synth-oper: handle const array array concat.Tristan Gingold2019-10-131-16/+41
* synth-oper: add more operations (float div, less for arrays)Tristan Gingold2019-10-131-7/+39
* synth-stmts: improve support for associations in function calls.Tristan Gingold2019-10-131-19/+92
* synth-inst: minor refactoring.Tristan Gingold2019-10-131-3/+2
* synth-oper: handle unsigned unsigned mul.Tristan Gingold2019-10-131-0/+13
* synth-expr: handle integer type conversion.Tristan Gingold2019-10-131-1/+4
* synth-expr: handle range array attribute in slices.Tristan Gingold2019-10-131-42/+74
* vhdl-annotations: handle list of record elements declaration.Tristan Gingold2019-10-131-2/+4
* vhdl: recognize std_logic_unsigned.conv_integer.Tristan Gingold2019-10-133-2/+12
* netlists-iterators: avoid a crash if no ports.Tristan Gingold2019-10-131-3/+1
* netlists-dump: improve output.Tristan Gingold2019-10-131-9/+28
* netlists-builders: adjust names of dyn_extract ports.Tristan Gingold2019-10-131-2/+2
* Show error on wait without condition (#976)Pepijn de Vos2019-10-131-0/+4
* add record (in)equality (#975)Pepijn de Vos2019-10-131-2/+4
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-115-23/+40
* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-117-18/+69
* vhdl: recognize minus from std_logic_unsignedTristan Gingold2019-10-113-1/+17
* vhdl: do not try to recognize mentor version of std_logic_arith.Tristan Gingold2019-10-101-0/+7
* synth: remove synth-typesTristan Gingold2019-10-104-91/+13
* netlists: add internings child package.Tristan Gingold2019-10-103-14/+61
* ghdlsynth: add --out=none to not display the result.Tristan Gingold2019-10-101-1/+6
* netlists-disp_vhdl: fix pasto on id_asr.Tristan Gingold2019-10-101-5/+5
* vhdl: improve error message for redefinition of libraryTristan Gingold2019-10-101-1/+1
* synth: handle constants for enum equality.Tristan Gingold2019-10-101-1/+5
* netlists: give a name to the free module.Tristan Gingold2019-10-101-2/+4
* synth: rewrite cleanup pass.Tristan Gingold2019-10-107-68/+188
* synth-decls: ignore use clauses.Tristan Gingold2019-10-101-0/+2
* synth-opeer: extend synth_uresizeTristan Gingold2019-10-101-1/+1
* synth-oper: handle more operators.Tristan Gingold2019-10-101-3/+6
* vhdl: recognize conv_unsigned from ieee.std_logic_arith.Tristan Gingold2019-10-106-4/+206
* synth: set name on generate statements.Tristan Gingold2019-10-092-6/+16
* synth: set location on instances.Tristan Gingold2019-10-091-0/+1
* synth: use synth.source for setting location.Tristan Gingold2019-10-098-17/+34
* netlists-disp_vhdl: handle const_SB32Tristan Gingold2019-10-091-1/+2
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